Shung, C.S. et al., "An Integrated CAD System for AlgorithmSpecific IC Design", Proc. Intl. Conf. on System Design 1989, Hawaii  Home/Search   Document Not in Database   Summary   Related Articles   Check

....memory, chip NO, and computation hardware is obtained. Next, a suuctural description is derived using some novel scheduling and hardware allocation algorithms. Tbe final slructure is then mapped Into hardware (macro cells or gate arrays) and generated using the Lager IV silicon assembly system [Shu89]. SInce high efficiency and optimal performance is a must, the system allows for user interfemnc and entry at every level of abstraction. An overview of the entire HYPER system is shown in Figure 1. hardw e Scheduling memory I . connectivity I , Assignment . DI FG t (d ....

C.S. Shung, et al., "An Integrated CAD System for AlgorithmSpecific IC Design," Interna#onal Conference On System Design, Hawaii,

....or layout design style. VIII. EXPERIMENTAL RESULTS To evaluate the proposed scheme, we have experimented with designs selected from the examples provided with the HYPER system [16] 24] and HLS benchmarks [31] 32] For RTL components, we have used the 2. 0 m dpp library resident in LagerIV [33]. The designs include several Avenhaus IIR filters of different structures (wdf, cascade, and parallel) an eleventhorder FIR filter (fir11) a seventh order IIR filter (iir7) a fifthorder elliptic filter (elliptic) a decimate by four filter (decby4) a filter for noise canceling (noisecancel) ....

C. B. Shung, R. Jain, E. Wang, K. Rimey, M. B. Srivastava, B. C. Richards, E. Lettang, S. K. Azim, L. Thon, P. L. Hilfinger, J. M. Rabaey, and R. W. Brodersen , "An integrated CAD system for algorithm-specific IC design," IEEE Trans. Computer-Aided Design, vol. 10, pp. 447--463, Apr. 1991.

....system consists of two interacting components namely datapath and controller. The datapath is built from the modules of the module library and the controller is a finite state machine implemented either as a PLA or a microprogram. Behavioral Synthesis is followed by logic [4] and layout synthesis [22] resulting in fabricatable mask layouts targeted for various technologies. During logic and layout synthesis, each data path module will be mapped to a network of gate level modules which will be eventually bound to standard cells. The controller will be processed by the logic and layout ....

.... steps to yield a pla implementation: 1) Derives boolean functions for the outputs as well as the next state bits; 2) Performs standard two level and multi level logic minimization [92] yielding a set of reduced equations; and (3) Generates a pla implementation by invoking pla layout generators [22]. The inputs and outputs of a controller have a direct correspondence with the implemented pla s inputs and outputs respectively. The number of feedback lines is dependent on the 29 pla.data 5 10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 0 10 20 30 40 50 60 70 Outputs ....

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Rajeev Jain et al., "An Integrated CAD System for Algorithm-Specific IC Design ", IEEE Transactions on Computer Aided design, Vol 10, No. 4, April 1991.

....Find, sort and search chip 5. Shuffle Exchange Network [35] 6. Traffic light controller Table 3 shows the behavioral specification data. pdss system is implemented in C on Sun Sparcstation platforms. Each register level design produced by pdss is processed by the Lager IV silicon compiler [36] to generate mask layouts. The designs generated use a two phase non overlapping clocking scheme. Although the designs are generated in a scalable cmos technology, all results for this paper are 19 Sl. Design Clock Nodes Transistors Area Cycles Simulation Period (sq.mm. Time (min) 1. Compress ....

Rajeev Jain et al., "An Integrated CAD System for Algorithm-Specific IC Design ", IEEE Transactions on Computer Aided design, Vol 10, No. 4, April 1991.

....is a conclusion derived more from the lack of observable uses of automated behavioral synthesis systems in commercial domains, rather than from the lack of existing systems in research and academia. Although it certainly can not be denied that progress has been considerable in this research area [Sh89] [DeRa86] BrCa88] a practical solution to the problem of automating behavioral synthesis is still distant [CaWo91] To develop a feasible approach to the problem, we have substituted the goal of a completely automated, push button synthesis system with one which attempts to maximally utilize ....

Shung, C., et al., "An Integrated CAD System for Algorithm-Specific IC Design," Proc. Int'l Conf. System Design, Jan., 1989. 47

....step are bound. When we compute power costs of all the feasible bindings, we consider swapping of input operands and select a solution with minimum cost. 5. Experimental Results For automatic generation of the layout, we designed partially guarded circuitry for Lager IV layout synthesis tool [12]. We implemented our boundary positioning algorithm and operation binding algorithm using C under UNIX environment. To measure power consumption, we developed a power estimation tool based on DBT model. We verified the reliability of the estimator by comparing the estimated power with the power ....

Brodersen, et al, "An Integrated CAD System for AlgorithmSpecific IC Design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, No. 4, pp. 447-463, April 1991.

....the high level synthesis community, only few authors have addressed this problem. Mimola [12] contains a retargetable code generator for a class of non DSP architectures. The 3 To be published in : Journal of VLSI Signal Processing, 1994. Copyright Kluwer Academic Publishers 1994. C to Silicon [13] and Cbc [14] compilers can generate microcode for programmable DSP architectures. The central idea behind both compilers is to investigate different data distribution strategies during the scheduling task, in a process called data routing. C to Silicon is based on a dedicated architectural model ....

C.B. Shung et al., "An integrated CAD system for algorithm-specific IC design," IEEE Trans. on CAD/ICAS , vol. CAD-10, no. 4, April 1991, pp. 447--463.

....550ns 5,602 11,458 20.3 2,662 17.44 4. FIFO 900ns 4,438 10,688 24.6 580 5.11 5. TLC 200ns 1,938 4,769 6.9 760 3.16 6. Shuffle Xchg 160ns 49,655 95,004 418.7 1,975 240 Table 5: Synthesized Design Data Each register level design produced by pdss is processed by the Lager IV silicon compiler [15] to generate mask layouts. The designs generated use a two phase non overlapping clocking scheme. Although the designs are generated in a scalable cmos technology, all results for this paper are obtained using 2 micron feature size. Switch level models are extracted from the layouts and simulated ....

Rajeev Jain et al., "An Integrated CAD System for Algorithm-Specific IC Design ", IEEE Transactions on Computer Aided design, Vol 10, No. 4, April 1991.

....interacting components namely datapath and controller. The datapath is composed of modules from the module library and the controller is a finite state machine implemented as a PLA microprogram. Behavioral Synthesis is followed by With TriQuest Design Automation. logic [3] and layout synthesis [4] resulting in fabricatable mask layouts targeted for various technologies. We present a novel profile based approach for behavioral synthesis to produce low power designs. Initially, for each module in the module library and for each size, average switching activity per input vector is ....

....# of Sched Carrs. Tran Synth. Scheds Length sitions Time (s) Decompress 1 13 13 52 1.0 Compress 1 14 15 53 1.0 Find 2 34 29 45 2.2 FIFO 2 10 29 57 1.7 TLC 2 17 18 27 1. 5 Shuffle 4 13 214 98 24.0 Each register level design produced by pdss is processed by the Lager IV silicon compiler [4] to generate mask layouts. The designs generated use a two phase non overlapping clocking scheme. Although the designs are generated in a scalable cmos technology, all results for this paper are obtained using 2 micron feature size. Switch level models are extracted from the layouts and simulated ....

Rajeev Jain et al., "An Integrated CAD System for AlgorithmSpecific IC Design ", IEEE Transactions on Computer Aided design, Vol 10, No. 4, April 1991.

.... steps to yield a pla implementation: 1) Derives boolean functions for the outputs as well as the next state bits; 2) Performs standard two level and multi level logic minimization [10] yielding a set of reduced equations; and (3) Generates a pla implementation by invoking pla layout generators [13]. The inputs and outputs of a controller have a direct correspondence with the implemented pla s inputs and outputs respectively. The number of feedback lines is dependent on the number of states and the state encoding. The number of terms realized in the pla depend on the amount of logic ....

Rajeev Jain et al., "An Integrated CAD System for Algorithm-Specific IC Design ", IEEE Transactions on Computer Aided design, Vol 10, No. 4, April 1991.

....control signals, and sequencing logic, handling subroutine addresses, figure 5. The external status signals ME, DE, S1 and S2 are used to handle conditional statements on both microinstruction and subroutine level. The layout of the processor has been generated using a place and route tool FLINT [8]. Finally the layout has been simulated at transistor level [9] before it was sent for processing in a 0.8 micron CMOS process. The die size, including the two lookup tables, is 6:5 Theta 7 mm 2 and contains approximately 65 000 transistors, figure 6. The lookup tables has been implemented as ....

C. B. Shung et al. "An Integrated CAD System for Algorithm-Specific IC Design". IEEE Trans. of Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-10, Apr. 1991, pp. 447--463.

....in this paper can guide the process. The designer evaluates a change in the architecture by retargeting the compiler and recompiling the program to observe the effect on the instruction count. A family of tunable processors has been developed by members of the Lager project 1 at Berkeley [1, 2]. 1 Lager also addresses high speed applications beyond the scope of the methodology described here. These processors use a horizontal instruction word: a vector of control signals with little or no restrictive encoding. Thus they are single level computers that execute a machine language ....

C.-S. Shung, An Integrated CAD System for Algorithm-Specific IC Design. PhD thesis, University of California at Berkeley, May 1988.

....confidence, devices that have manufacturing defects. The management of teams, design systems, designers within teams, and design tools within systems is a complex task. Design methodologies and design frameworks addressing parts of these issues continue to evolve as evidenced in the literature [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33]. The goal of achieving a unified or unifying design framework remains elusive, not only due to the overall complexities of the electronic design process, but also because of the largely proprietary nature of state of the art design methodologies and design flows. In this paper, we introduce a ....

C. B. Shung, et al. An Integrated CAD System for Algorithm-Specific IC Design. IEEE Transactions on Computer-Aided Design, 10(4):447--463, April 1991.

....of extra transitions is reduced. The capacitance switched for a chained implementation is a factor of 1.5 larger than the tree implementation for a four input addition and 2.5 larger for an eight input addition. The above simulations were done on layouts generated by the LagerIV silicon compiler [25] using the IRSIM [17] switch level simulator over 1000 uncorrelated random input patterns. The results presented above indicate that increasing the logic depth (through more cascading) will increase the capacitance due to glitching while reducing the logic depth will increase register power. Hence ....

....such as placement, floorplanning and global and detailed routing. Of course, an accurate model for such a complex system can be built only when a particular set of design tools is targeted. As mentioned earlier, we targeted the HYPER high level synthesis tools and the Lager IV silicon assembler [25]. We used the scalable CMOS design rules provided by Mosis and targeted feature sizes of 1.2 m and 2 m. The selection of this particular suit of design tools, enabled us to somewhat simplify the estimation process. We concentrated our attention only on the inter block (between macro blocks, e.g. ....

C. S. Shung et. al., "An Integrated CAD System for Algorithm-Specific IC Design.", IEEE Transactions on CAD of Integrated Circuits and Systems, April 1991.

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Shung, C.S. et al., "An Integrated CAD System for AlgorithmSpecific IC Design", Proc. Intl. Conf. on System Design 1989, Hawaii

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C. B. Shung et al., "An integrated CAD system for algorithm-specific IC design," IEEE Trans. Computer-Aided Design, vol. 10, pp. 447--463, Apr. 1991.

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C. S. Shung et. al., "An Integrated CAD System for Algorithm -Specific IC Design.", IEEE Transactions on CAD of Integrated Circuits and Systems, April 1991.

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. C.S. Shung, et al., "An Integrated CAD System for Algorithm-Specific IC Design," International Conference on System Design, Hawaii, January 1989.

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Rajeev Jain et al., "An Integrated CAD System for Algorithm-Specific IC Design ", IEEE Transactions on Computer Aided design, Vol 10, No. 4, April 1991.

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C. Shung et al., "An integrated CAD system for algorithm-specific IC design", IEEE Trans. Comp.-Aided Design, Vol. 10, No. 4, April 1991, pp. 447--463.

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C. Shung et al., "An integrated CAD system for algorithm-specific IC design", IEEE Trans. Comp.-Aided Design, Vol. 10, No. 4, April 1991, pp. 447--463.

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