P. Landman and J. Rabaey, "Power Estimation for High Level Synthesis," Proceedings of EDAC-EUROASIC `93, Paris, France, pp. 361-366, February 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....as transition density [8] are proposed. In a statistical technique [9, 10] the circuit is simulated with randomly generated input vectors until power converges to the average power where convergence is tested by statistical mean estimation techniques. At the architectural level, Landman et al. [11] pre VHDL Simulator Profiling Stimuli DFG Extraction Scheduling and Performance Estimation Register Optimization Interconnect Optimization Controller Generation Module Library Probes VHDL with DFG with Profile Data Profile Data Constraints Profiler Behavioral Specification ....

Paul Landman and Jan Rabaey, "Power Estimation for High Level Synthesis", Proc. of EDAC-EUROASIC, pp 361366, February 1993.

....actual input switching activities in order to provide power estimates which are sensitive to the input activities. In [51] and [34] the model consists of a single physical capacitance value and a single switching activity value which represents the average switching activity on each input bit. In [35], a more detailed model is presented where it is projected that data in the datapath of a digital system can be divided into two regions: the Least Significant Bits (LSB) which act as uncorrelated white noise and the Most Significant Bits (MSB) which correspond to sign bits and exhibit strong ....

P.E. Landman and J. Rabaey. " Power estimation for high level synthesis. " In Proceedings of the European Conference on Design Automation, pages 361-366, February 1993.

....of an algorithm and a library of hardware modules, explores the space of the available solutions for different values of clock periods and supply voltages. The results have been compared with an architectural level power estimator, called Stochastical Power Analysis (SPA) and proposed in [11], on 23 different chips, showing an average error of approximately 20 . Other power estimation techniques based on high level descriptions have been proposed in [11, 12, 13] The techniques described in [11] targeting data path architectures, derive stochastic models of busses and internal ....

....The results have been compared with an architectural level power estimator, called Stochastical Power Analysis (SPA) and proposed in [11] on 23 different chips, showing an average error of approximately 20 . Other power estimation techniques based on high level descriptions have been proposed in [11, 12, 13]. The techniques described in [11] targeting data path architectures, derive stochastic models of busses and internal modules from the statistical behavior of inputs. In [12] a power estimation model for data path architectures operating at the RT level is described. The model accounts for the ....

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P.E. Landman and J.M. Rabaey, Power Estimation for High-Level Synthesis, in: Proc. EDAC-EUROASIC '93 European Design Automation Conference, (Paris, 1993) 361-366.

.... Search [Fri90, Glo89] Most recently, a new probabilistic algorithm has been proposed, where the solution is iteratively built, instead of improved [Won01] Wide estimation techniques can be used at all stages of the design process to predict the tree main metrics of design speed, area, and power [Rab94, Lan93, Ver94, Con99]. Preliminaries Filters are functions or devices that implement a function that transforms a given sequence of input number according to a given rule into a sequence of output numbers. In particular they are often used to extract a certain part of the frequency spectrum from an input signal. ....

P. E. Landman and J. M. Rabaey, Power Estimation for High Level Synthesis, European Conference on Design Automation, pp. 361-366, 1993.

....circuit [1] a structural transformation based approach holds great promise for low power design. In this paper, we describe an efficient estimation tool that can be employed in high level synthesis for power optimization. Although a number of power estimators have been reported in the literature [1, 3, 4, 5, 9, 12, 7], with the exception of [1] 5] and [12] the others require the circuit to be specified at gate level. While flattening an RTL netlist into a gate level netlist is by itself a cumbersome task, gate level power estimators place excessive run time and memory requirements. Estimators reported in ....

....holds great promise for low power design. In this paper, we describe an efficient estimation tool that can be employed in high level synthesis for power optimization. Although a number of power estimators have been reported in the literature [1, 3, 4, 5, 9, 12, 7] with the exception of [1] [5], and [12] the others require the circuit to be specified at gate level. While flattening an RTL netlist into a gate level netlist is by itself a cumbersome task, gate level power estimators place excessive run time and memory requirements. Estimators reported in [1] and [12] provide approximate ....

[Article contains additional citation context not shown here]

P. Landman and J.Rabaey. Power estimation for high level synthesis. In Proceedings of EDACEUROASIC '93, pages 361--366, 1993.

.... of functional units on which operations are implemented (resource selection) On behavioral level, the power consumption of di erent implementation alternatives can be estimated as a function of the input switching activity either using a parametric analytical model or a look up table based model (Landman and Rabaey, 1993, 1994; Landman, 1994) Such models can be used to guide resource selection in choosing modules that optimally trade o area vs. performance vs. power to implement a given operation. Other ecient techniques for behavioral power optimization include the choice of number representation and bus ....

Landman, P. E. and Rabaey, J. M., Power Estimation for High-Level Synthesis, in Proceedings of the European Conference on Design Automation, pp. 361-366, 1993.

....models for the components. The idea is to simulate the circuit with randomly generated input vectors until power converges to the average power. The convergence is tested by statistical mean estimation techniques. 2. 2 Architectural Level of Abstraction At the architectural level, Landman et al. [41] presented a technique for the characterization of module library using signal statistics. Landman et al. 66] presented a methodology for low power design space exploration at the architectural level of abstraction. Black box power models for the architectural level components were generated [67] ....

Paul Landman and Jan Rabaey, " Power Estimation for High Level Synthesis", Proc. of EDAC-EUROASIC, pp 361-366, February 1993. 80

....data dependency of the power dissipation. For example, if one of the inputs to the multiplier is always one, we would expect the power dissipation to be less than the case when both inputs are changing randomly. In contrast, the stochastic power analysis technique proposed by Landman and Rabaey in [40] is based on an activity sensitive macro model, called the dual bit type model, which maintains that switching activities of high order bits depend on the temporal correlation of data, whereas lower order bits behave randomly. The module is thus completely characterized by its capacitance models ....

P. Landman and J. Rabaey, "Power estimation for high-level synthesis," in Proc. EDAC-93: IEEE Eur. Conf. Design Automation, Paris, France, Feb. 1993, pp. 361--366.

....power estimators display greater computational efficiency. Transistor and gate level power estimation techniques have been well researched [1, 2, 3, 4] and several commercial tools exist that are reasonably mature. While there has also been some research on high level power estimation techniques [5, 6, 7, 8, 9, 10, 11, 12], their limited accuracy has been one of the major challenges facing their widespread adoption. High level power estimators can be classified on the basis of the information they produce (e.g. spatial and temporal resolution of the power report) as well as the techniques employed (e.g. fast ....

P. Landman and J. Rabaey, "Power estimation for high-level synthesis, " in Proc. European Design Automation Conf., pp. 361--366, Feb. 1993.

....as transition density [16] are proposed. In a statistical technique [2, 3] the circuit is simulated with randomly generated input vectors until power 2 converges to the average power where convergence is tested by statistical mean estimation techniques. At the architectural level, Landman et al. [8] presented a technique for the characterization of module library using signal statistics. At the behavioral level, Chandrakasan et al. 4, 5] present a high level synthesis system, HYPER LP, which minimizes power consumption in application specific data path intensive CMOS circuits using a ....

Paul Landman and Jan Rabaey, "Power Estimation for High Level Synthesis", Proc. of EDACEUROASIC, pp 361-366, February 1993.

....proposed. Statistical techniques [22, 23] do not require any specialized models for components. The circuit is simulated with randomly generated input vectors until power converges to the average power. The convergence is tested statistical techniques. At the architectural level, Landman et al. [24] presents a technique for the characterization of module library using signal statistics. At the behavioral level, Chandrakasan et al. 25, 26] present a high level synthesis system, HYPERLP, which minimizes power consumption in application specific datapath intensive CMOS circuits using a ....

Paul Landman and Jan Rabaey, " Power Estimation for High Level Synthesis", Proc. of EDAC-EUROASIC, pp 361-366, February 1993.

....simulation techniques are too slow to be used in practice. In order to enable fast estimation, the power consumed by a library element is modeled as a function of selected input and output statistics. Methods to model selected circuit components such as adders, ALUs, memories, etc. can be found in [21]. For our work, we use the model proposed in [5] A brief description of the model is included here for the sake of completeness. The power consumed by a library element is modeled as a weighted sum of the activities on its input bits. The CDFG is first simulated with typical input traces. For ....

P. Landman and J. Rabaey, "Power estimation in high level synthesis," in Proc. EDAC-EUROASIC, pp. 361--366, Feb. 1993.

....have been used for power estimation. Since transistor level simulation is too slow for use with large designs, logic level simulation was proposed (Irsim) Even this does not allow fast exploration. An architectural power estimator based on profiling and state trace is described in [4] Landman [7] proposes a modeling approach for module characterization. Mehra and Rabaey [8] address the problem of estimating power from a behavioral description using a combination of analytical and stochastic techniques. A profile driven approach is presented for low power behavioral synthesis by Kumar in ....

P. Landman, J. Rabaey, Power Estimation for High Level Synthesis, Proc. EDACEuroASIC, Feb. 1993

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P. Landman and J. Rabaey, "Power Estimation for High Level Synthesis," Proceedings of EDAC-EUROASIC `93, Paris, France, pp. 361-366, February 1993.

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P. Landman, J. Rabaey, "Power Estimation for High-Level Synthesis," EDAC-93: IEEE European Conference on Design Automation, pp. 361-366, Paris, France, February 1993.

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P. Landman, J. Rabaey, `Power Estimation for High Level Synthesis', in Proc. European Design Automation Conference, pp. 361-366, Feb.1993.

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P. Landman and J. Rabaey, "Power Estimation for High Level Synthesis," Proceedings of EDAC-EUROASIC `93, Paris, France, pp. 361-366, February 1993.

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P. Landman and J. Rabaey. "Power estimation for high-level synthesis, " Proceedings of IEEE European Design Automation Conference, February 1993, pages 361--366.

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P. Landman, J. Rabaey, "Power Estimation for High-Level Synthesis, " EDAC-93: IEEE European Conference on Design Automation, pp. 361-366, Paris, France, February 1993.

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P. Landman, J. Rabaey, "Power Estimation for High-Level Synthesis," IEEE EDAC-93, pp. 361-366, Paris, France, Feb. 1993.

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P.E. Landman and J. Rabaey. " Power estimation for high level synthesis. " In Proceedings of the European Conference on Design Automation, pages 361-366, February 1993.

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P. E. Landman and J. M. Rabaey. Power estimation for high level synthesis. In Proceedings of the European Conference on Design Automation, pages 361-- 366, February 1993.

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P.E. Landman and J. Rabaey. " Power estimation for high level synthesis. " In Proceedings of the European Conference on Design Automation, pages 361-366, February 1993.

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P. L. Landman and J. M. Rabaey. Power estimation for high level synthesis. In Proc. of EDAC-EUROASIC'93, Paris, pages 361--366, February 1993.

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Paul Landman and Jan Rabaey, "Power Estimation for High Level Synthesis", Proceedings of EDAC-EUROASIC, pp 361-366, February 1993.

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