A. Salz and M. Horowitz, "IRSIM: An Incremental MOS Switch-Level Simulator," Proceedings of the 26th Design Automation Conference, pp. 173-178, 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of the CCR s transistors, we wish to compute the effects on the CCRs internal nodes. This computation requires 3 phases: affected node identification, steady state (DC) value computation, and delay computation. 3. 2 IRSIM We have chosen to implement a symbolic version of the timing simulator IRSIM[21]. IRSIM is itself derived from two earlier simulators, RSIM and nRSIM. RSIM[24] introduced the concept of event driven switch level timing simulation based on Elmore delays[13, 20] which are delay estimates computed as RC products. It models transistors as switched linear resistors and all ....

A. Salz and M. A. Horowitz. IRSIM: An Incremental MOS Switch-level Simulator. Proceedings of the Design Automation Conference, pages 173--178, June 1989.

....tools [13] and Lager synthesis tools [14] using standard cells developed for the ERIF chip. These standard cells have been modified previously to fit sub micron processes. Functionality of the TMIC was verified by Powerview simulations using Lager standard cell VHDL models and Berkeley IRSIM [15] at the transistor switch level. Both simulations indicate this chip was fully functional at the system clock requirement of 50 MHz. An initial lot of 5 TMC die were packaged in 40 pin DIPs for low cost functionality testing. Upon successful results from this test, the remaining TMC die were ....

A. Salz, M. Horowitz, 'IRSIM: an incremental MOS switch-level simulator, Proceedings of the 26th Annual. ACM/IEEE Design Automation Conference, 1989, pp. 173-178.

....the execution time in seconds required by the optimization procedure to complete. Power estimates within the kernel extraction procedure have been computed using symbolic simulation [30] while those for the initial and final circuits have been determined using the Irsim switch level simulator [31], assuming a clock frequency of 100 MHz. Results are very encouraging. An average power savings of approximately 51 has been achieved with peaks of more than 80 . Notice that some circuits of the complete suite are missing in the table, namely, and . These circuits have the peculiar ....

A. Salz and M. Horowitz, "IRSIM: an incremental mos switch-level simulator, " in Proc. ACM/IEEE Design Automation Conf., Las Vegas, NV, June 1989, pp. 173--178.

....5: Transmitter channel these two approaches to design. The entire chip was designed by the author; accordingly, the level of design skill is comparable for both the synchronous and asynchronous portions. Furthermore, both parts were designed using the same tools (magic [12] CAzM [4] irsim [14], and Synchronized Transitions [17] and with the same criteria: to be fast and simple. On the other hand, the STARI chip performs little actual computation. This means that pipelining and handshaking overhead figure prominently in the comparison. In the context of the STARI chip, synchronous ....

Arturo Salz and Mark Horowitz. IRSIM: An incremental MOS switch--level simulator. In Proceedings of the 27th ACM/IEEE Design Automation Conference, pages 173--178, Los Vegas, NV, June 1989.

....considers effects like glitching which are hard to capture in nonsimulative techniques. Simulative techniques could be applied at various levels of design flow depending on the degree of accuracy and speed desired. For example circuit level and switch level simulators are extremely accurate [45], 53] Notable contribution to simulation based power estimation technique was given by Najm in [79] 78] 58] 58] describes a new stochastic measure of switching activity called transition density and describe a fast algorithm for computing the transition density of internal nodes, given the ....

A. Saltz and M. Horowitz. "IRSIM: An Incremental MOS Switch-level Simulator ". In Proc. Design Automation Conference, pages 173--178, 1989.

....and single step nonlinear iteration) to increase the speed by two to three orders of magnitude over SPICE. Switch level simulation techniques are in general much faster than circuit level simulation techniques, but are not as accurate or versatile. Standard switch level simulators (such as IRSIM [59]) can be easily modified to report the switched capacitance (and thus dynamic power dissipation) during a simulation run. Verilog XL logic simulator is a Verilog based gate level simulation program that relies on the accuracy of the macromodels built for the gates in the ASIC library as well as ....

A. Salz and M. A. Horowitz. " IRSIM: An incremental MOS switch-level simulator. " In Proceedings of the 26th Design Automation Conference, pages 173-178, June 1989.

....abstractions of signals rather than with voltage and current waveforms in order to run fast enough. Unfortunately, nominally digital designs can contain analog components. An example of an analog circuit in a wholly digital chip would be a sense amplifier. A fast, digital simulator like IRSIM [17] or COSMOS [18] cannot correctly model the functional behavior of some sense amplifiers, let al..one their performance. Since top level simulations typically address functional behavior only as a check on proper module interconnection, IRSIM could perform that functional check if sense amplifiers ....

A. Salz and M. Horowitz, "IRSIM: An Incremental MOS Switch-Level Simulator ", Proc. 26th Design Automation Conference, 173-178, 1989. 91

....Fig. 6. As a consequence of employing a pipelined structure, the modulator layout is simplified into a regular datapath rather than complex custom cells or synthesized logic. Fig. 8 shows the simulated output power spectrum of the digital modulator obtained using the switch level simulator, IRSIM [15]. The clock rate was 120 MHz and the circuits were operated using a single 2.5 V power supply. The modulator achieves greater than 98 dB (16 bits) of dynamic range for a signal bandwidth of 5 MHz, which corresponds to an oversampling ratio of 12. The digital modulator was overdesigned so that the ....

....feedthrough of these signals into the analog output. Furthermore, these inputs are generated with a high crossing point, as illustrated in Fig. 12, to ensure that there is no time when both switching transistors are off, thereby avoiding significant transients at the tail node of the switch [15]. To implement the low swing, high crossing point digital signals with levels that are independent of process technology variations, the all PMOS driver shown in Fig. 13 is used. This circuit is preceded by flip flops used to synchronize the digital inputs to the current cells, and it directly ....

Arturo Salz and Mark Horowitz,"IRSIM: An Incremental MOS Switch-level Simulator," 26th annual ACM/IEEE design automation conference digest of papers, pp 173-178, June 1989.

....Area and power are computed after mapping the gate level netlist to a technology based on a 1.0m HP CMOS26B process. Circuit area is expressed in terms of the weighted number of gates in the circuit (with 2 input gates normalized to 1) while power consumption is measured by means of IRSIM [13], assuming a clock frequency equal to 20 MHz, and a power supply voltage of 5 V. Table 1 reports the results of the various optimization algorithms on the subset of fullscan ISCAS 89 circuits adopted in [9] In all experiments, a 32 bit primitive LFSR was used as a TPG, with a suitable test ....

A. Salz, M. Horowitz, "Irsim: An incremental mos switch-level simulator", ACM/IEEE Design Automation Conference, 1989, pp. 173-178

....Step II : Extraction of nsc values in a prototype pla For a given prototype pla an input vector sequence is applied to switch nodes in the pla . Capacitance switched by each node(s) is observed, and nsc for all sub components is computed. The capacitance can be measured by tools such as IRSIM [98], SPICE or PowerMill [97] In this work, we used IRSIM CAP a modified version of IRSIM switch level simulator for improved capacitance measurements. 31 The following input vector sequence ( 0,0,0,0) 1,0,0,0) 1,1,0,0) 1,1,1,0) 1,1,1,1) could be applied to the above (4,4,4) pla example. ....

A. Salz and M. Horowitz, "IRSIM: An Incremental MOS Switch-Level Simulator", Proceedings of the 26th Design Automation Conference, pp. 173-178, 1989.

....used for the experiments contained NAND and NOR gates with up to four inputs, buffers, and inverters. Each cell had 3 different size drive options. Power values of the initial and final circuit implementations were obtained through transistor level simulation of 10,000 random vectors using Irsim [15]. All the experiments were run on a DEC AXP 1000 300 with 128 MB of main memory. As mentioned in the introduction, the clock gating transformation performs best on reactive circuits, i.e. circuits with a large number of idle conditions. We examined the entire Iscas 89 synchronous sequential ....

A. Salz, M. Horowitz, "IRSIM: An Incremental MOS Switch-Level Simulator," DAC-26: ACM/IEEE Design Automation Conference, pp. 173-178, Las Vegas, NV, June 1989.

....simulating the switching level module using a very long stream of randomly generated input patterns and monitoring the capacitance switched per pattern, until convergence occurs as discussed below. The capacitance measurements are carried out by IRSIM CAP [37] which is a modified version of IRSIM [38] switch level simulator for better capacitance measurements. Let C k be the total capacitance charged after applying k random input patterns without reinitialization between successive patterns. Z k = Ck k denotes the average capacitance per input pattern after applying k patterns. ffi k = jZ ....

A. Salz and M. Horowitz, "IRSIM: an incremental MOS switch-level simulator," in Proc. Design Automation Conf., pp. 173-178, June 1989. 25

....out the issue of the instructions to the Functional Units. The read ports of the various control bits inside the IS are also opened up to indicate the type of the instruction being issued. Chapter 5 Simulation and Results 5.1 Simulation 5.1.1 Simulation tools The IRSIM version 8. 6 simulator [14] is used to simulate the layout and verify its functionality. The event driven logic level simulator for MOS circuits models the transistor as a resistor in series with a voltage controlled switch and each node with a capacitance. It uses the Chorng Yeoung Chu s model to compute the delays and ....

A. Salz and M. Horowitz. IRSIM: An Incremental MOS Switch-Level Simulator. In Proceedings of the 26th Design Automation Conference, pages 173--178, Las Vegas, Nevada, June 1989.

....our boundary positioning algorithm and operation binding algorithm using C under UNIX environment. To measure power consumption, we developed a power estimation tool based on DBT model. We verified the reliability of the estimator by comparing the estimated power with the power obtained by IRSIM [13], a switch level simulator, running on the simulation file extracted from the layout generated by Lager IV. We used 1.2 micron technology for the generation of layouts. We tested our algorithm using well know data dominated circuit examples from HYPER [14] We first performed behavioral simulation ....

A. Salz and M. Horowitz, "IRSIM: An Incremental MOS Switch-Level Simulator," Proceedings of Design Automation Conference, pp. 173-178, 1989.

....An annotated CDFG is then obtained through HLS process including the continuous time domain scheduling and control synthesis. Finally after RTL netlist generation, a layout is generated by a placement routing tool in LagerIV using double metal layers, and the layout is veri ed by a simulator IRSIM [15]. For post layout design analysis, layout parasitic elements are extracted from the layout, and the delays are calculated. 6 Conclusion In this paper, we have proposed a technique of layout driven performance optimization, which incorporates the post layout physical aspects into HLS process. ....

A. Salz and M. Horowitz, \IRSIM: an incremental MOS switch-level simulator," in Proc. Design Automat. Conf., 1989, pp. 173-178.

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A. Salz and M. Horowitz, "IRSIM: An Incremental MOS Switch-Level Simulator," Proceedings of the 26th Design Automation Conference, pp. 173-178, 1989.

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A. Salz and M. A. Horowitz. IRSIM: An incremental MOS switch-level simulator. In Proceedings of the 26th Design Automation Conference, pages 173--178, June 1989.

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A. Salz and M. A. Horowitz. " IRSIM: An incremental MOS switch-level simulator. " In Proceedings of the 26th Design Automation Conference, pages 173-178, June 1989.

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A. Salz and M. Horowitz. IRSIM: An Incremental MOS Switch-Level Simulator. In Proceedings of the 26  Design Automation Conference, pages 173--178, June 1989.

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A. Salz and M. A. Horowitz. IRSIM: An Incremental MOS Switch-level Simulator. Proceedings of the Design Automation Conference, pages 173--178, June 1989.

No context found.

Arturo Salz and Mark Horowitz, "IRSIM: An incremental MOS switch-level simulator," in Proceeding of the 26th Design Automation Conference, 1989, pp. 173--178.

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A. Salz and M. Horowitz, "IRSIM: An incremental MOS switch-level simulator," in Proc. DAC-26: ACM/IEEE Design Automation Conf., Las Vegas, NV, June 1989, pp. 173--178.

No context found.

A. Salz and M. Horowitz, "IRSIM: An incremental MOS switch-level simulator," in DAC-26: ACM/IEEE Design Automation Conf., June 1989, pp. 173--178.

No context found.

A. Salz and M. Horowitz, "IRSIM: an incremental MOS switch-level simulator," in Proc. Design Automation Conf., pp. 173-178, June 1989.

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A. Salz and M.Horowitz,"IRSIM: An Incremental MOS Switch-Level Simulator", Proceedings of 26th DAC,pp. 173-178,1989.

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