B.S. Haroun and M.I. Elmasry. " Architectural Synthesis for DSP Silicon Compilers". In IEEE Trans on CAD, pages 431--447, Apr 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....synthesis systems that were proposed. These systems were followed by others with more comprehensive set of algorithms. 64] proposes a hardware compiler called Flamel that takes programs written in Pascal and generates optimized hardware by identifying parallelism in them. Haroun and Elmasry in [50] present SPAID: A novel design methodology for DSP algorithm synthesis. Various transformations in SPAID include pipelining, retiming etc which made it an efficient synthesis engine of its time. Another very important high level synthesis system was Cathedral [22] 15] It takes behavioral ....

B.S. Haroun and M.I. Elmasry. " Architectural Synthesis for DSP Silicon Compilers". In IEEE Trans on CAD, pages 431--447, Apr 1989.

....iteration time of 16. The schedule for the FIR filter with an initiation interval of 15 is given in Figure 15. In terms of the iteration time, TLS performs better than Theda.Fold. TLS CPU time varies between 0.5 and1sfortheFIRfilter. 3.2. The fifth order elliptical wave filter benchmark The EWF [3, 39] consists of 34 operations (eight multiplications and 26 additions) and it is the most extensively cited benchmark example in high level synthesis. Like the previous work, we assume that an addition takes one cycle to execute and a multiplication takes two cycles to execute on a non pipelined ....

Haroun, B. S. and Elmasry, M. I. (1989) Architectural synthesis for DSP silicon compiler. IEEE Trans. ComputerAided Design Integrated Circuits Syst., 8, 431--447.

....the binding. Their binding algorithm will only be valid if execution delays of functional units and registers dominate interconnection delays. 2.2 Embedded Memory Architectures Several systems have been developed which allocate the datapath directly for the final memory architecture. SPAID [16] and STAR [17] consider register files and a linear topology directly. Whereas a unique bus is connected to each register file in SPAID, every register file can be connected to every bus as required by the allocation results in STAR. Balakrishnan et al. 18] proposed an approach of grouping ....

....for Register File based Architectures. Table 8 shows the comparison of allocation results of the EWF example for register file and linear topology architectures. A two phase clocking scheme was assumed in these allocations. Table 8(a) compares our allocation results with the results of SPAID [16]. We used a result of our scheduler as the input for this allocation. MandM produced better results than SPAID for each of the different designs. Notably, MandM needed a far fewer number of buses, registers, and multiplexer inputs. This is due to the following features of MandM: 1) Any register ....

Haroun, B. S. and Elmasry, M. I., "Architectural Synthesis for DSP Silicon Compilers," IEEE Trans. on Computer-Aided Design, vol.8, no.4, pp.431-447, Apr. 1989.

....delay estimation using a layout driven approach. Reference [10] used area time models to predict design tradeoffs from the DFG graph. However, their model considers only functional units at the scheduling level and does not include RTL components such as registers, multiplexers and ALUs. SPAID [11] also determines the clock period by considering delay of components and finding the worst datapath delay, but it does not take into account the wiring delay. In BUD system [12] the wire lengths are obtained from a floorplanner and the wiring delay is computed using a simple RC model. CHIPPE [13] ....

B. Haroun and M. Elmasry, "Architectural Synthesis for DSP Silicon Compiler," IEEE Trans. on CAD, April 1989.

....after merging nodes x and y. In the pseudo code shown in Figure 1, this corresponds to the else portion that selects the second node y and merges it with x and then modifies the graph accordingly. Observe how the sequent specifies all that is true about the else branch of the algorithm. Formulas [1] and [2] assert that the node set S 1 is nonempty and the neighbor set of the selected node sn is nonempty. The cardinality of the node set after merging two nodes is always less than the cardinality of the original node set and this is expressed in Formula f 4g. Formula f 5g is identical to ....

....and execute some basic proof commands in PVS. Thus, the implication in Formula f 6g can be eliminated and the right hand side would be available as a separate formula. This formula states that the well formed property holds for a set of nodes in which, nodes 10 wellformed.2. 2 : [ 1] selectmatch(sn, S 1, E 1) sm [ 2] selectnode(CG 1) sn [ 3] S 1, E 1) cs 1, HP 1) CG 1 f 4g card(PROJ1(PROJ1(mergenodes(sn, sm, CG 1) card(S 1) f 5g (cpa(mergenodes(sn, sm, CG 1) IR 1) FR 1) f 6g cpa( PROJ1(PROJ1(mergenodes(sn, sm, CG 1) PROJ2(PROJ1(mergenodes(sn, sm, ....

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B.S. Haroun and M.I. Elmasy. "Architectural Synthesis for DSP Silicon Compilers". In Transactions on CAD, pages 431--447. IEEE, April 1989.

....system should integrate both sets of subproblems. However, to reduce computational complexity most high level synthesis systems decouple them. Older HLS systems synthesized the execution unit first and then the storage and data transfer subsystem without considering their interdependence [9, 10, 11]. This could prematurely prune the search space for storage and data transfer subsystem synthesis. More recent HLS systems do consider the effects of operation scheduling and binding on the storage and data transfer subsystem [12, 3, 13] Most use an estimate of the minimum numbers of registers, ....

B. S. Haroun and M. I. Elmasry, "Architectural Synthesis for DSP Silicon Compilers," IEEE Transactions on Computer-Aided Design, vol. 8, pp. 431--447, April 1989.

....its small area contribution. These HLS systems usually synthesize the storage architecture and interconnect network in a secondary step after the execution unit has been synthesized. Some systems completely decouple execution unit synthesis from synthesis of the storage and data transfer subsystem [1, 2, 3]. Others use simple models for these subsystems to account for effects on them during the synthesis of the execution unit [4, 5, 6] Some HLS tools are specialized to generate extremely efficient architectures for algorithms that can be described as arrays and multidimensional loops [7, 5] ....

B. S. Haroun and M. I. Elmasry, "Architectural Synthesis for DSP Silicon Compilers," IEEE Transactions on Computer-Aided Design, vol. 8, pp. 431--447, April 1989.

....example, the hardware cost, as far as possible. To achieve good binding, several methods have been proposed. We can categorize these methods into five groups as explained in the following subsections: 1.1. 1 Constructive methods The operations are bound to RT components in a stepby step fashion[3, 4, 5]. A constructive algorithm starts with an empty datapath and builds the datapath gradually by adding FUs, storages, or interconnections as necessary. For each operation, the algorithm tries to find an FU on the partially designed datapath that is capable of executing the operation and also idle ....

B. Haroun and M. Elmasry, "Architectural synthesis for dsp silicon compilers," IEEE Transactions on Computer-Aided Design, pp. 431--447, April 1989.

....R4 V1 V1 V2 V3 V4 Figure 1 The Traditional Binding Model The form of data transfer allocation depends on the connection style used. In a general interconnection style [4,5] any interconnection structure of wires, buses, and multiplexers may be used used. In a bus oriented interconnection style [6], a restricted interconnection style is used in which module (register and functional unit) outputs drive one or more buses, which are connected by a single level of multiplexers to module inputs. In a point to point interconnection style [2] module outputs are connected to module inputs by a ....

B. Haroun and M. Elmasry, "Architectural Synthesis for DSP Silicon Compilers", IEEE Trans. CAD, Vol. 8, No. 4, pp. 431-447, April, 1989.

....the structure of the input specification. It is more or less directly compiled into silicon. This is possible, because only a small number of operations is mapped on the hardware. For example, the elliptic wave filter, which is frequently used as an example in high level synthesis (e.g. [ 74] [ 89] 114] 151] 213] has approximately 34 operations. These operations are mapped onto a datapath of more than 2 units. This means, less than 20 operations are mapped onto a unit. Therefore the hardware structure can be adapted directly to the communication pattern of the CDFG. The ....

B.S. Haroun and M.I. Elmasry. Architectural synthesis for DSP silicon compilers. IEEE Trans CAD, 8(4):431--447, April 1989.

....while scheduling. Most synthesis systems assume each function in a DFG to be implemented by a predetermined hardware processor. In this paper we perform automatic allocation of each operation to a library of processors. The problem of module selection during scheduling has been addressed [13] [14] [31] 33] in the context of heuristic scheduling. Module selection during scheduling by ILP was reported in [26] for scheduling large grain signal processing algorithms. In this paper we support fine grain signal processing algorithms. Each module in the library may be described by several ....

B. S. Haroun and M. I. Elmasry, "Architectural synthesis for DSP silicon compilers," IEEE Trans. Computer-Aided Design, vol. CAD-8, no. 4, pp. 431--447, Apr. 1989.

....at an early stage realized the necessity for formal design methods in order to create automatic ASIC design tools. Substantial research in this field has been carried out during the last decade, and various systems for Data Path and Controller Synthesis 1 have been constructed, examples are [9, 10, 11, 12, 13, 14, 15, 16]. These systems typically take as an input an executable behavioral specification formulated in terms of an applicative language, e.g. the DSP oriented Silage language [17] Based on the behavioral description, as well as on various 1 Normally refered to as High Level Synthesis. CHAPTER 1. ....

....we have not be able to find any paper, text book, or technical report describing such a library. In the High Level Synthesis community, researchers defined in the early days one very popular benchmark example for comparison of their scheduling algorithms the 5 th order Digital Wave Filter, [13]. However, based upon this example we cannot make fair comparisons with these earlier works basically because the HLS scheduling strategies are assigning atomic operations onto a heterogeneous target architecture composed of execution units (EXU) like ALUs, multipliers, shifters, etc. This ....

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B. S. Haroun and M. I. Elmasry. Architectural Synthesis for DSP Silicon Compilers. IEEE Trans. Computer-Aided Design, vol. 8, no. 4, April 1989. pp. 431-447. BIBLIOGRAPHY 130

....algorithms constrained by the TMS32010 data path. 2. Previous Work Previous efforts in data path synthesis used models that can be divided into two major types: In the first type, a register and multiplexer bus transaction model is derived for the particular communications of the designs [5][10] 11] 12] This model is typically represented as a connection graph and conventional graph search and matching techniques are applied. More recent models accommodate register files but restrict the connectivity [15] The second type uses a pre defined data path and generates microcode or ....

B.S. Haroun, M.I. Elmasry, "Architectural Synthesis for DSP Silicon Compiler", IEEE Trans. CAD/ICAS, pp. 431-447, April 1989.

....in High level Synthesis Over the last few years, several high level synthesis systems have incorporated comprehensive sets of transformations, coupled with powerful optimization strategies. Example systems with elaborate applications of transformations are Flamel [8] SAW [9] SPAID [10], HYPER [11] and CATHEDRAL [12] Among the set of transformations used by the Flamel design system are loop transformations, height reduction and constant propagation. SAW uses among other transformations in line expansion, dead code elimination, four types of transformations for conditional ....

B.S. Haroun, M.I. Elmasry, "Architectural Synthesis for DSP Silicon Compilers", IEEE Transaction on CAD for IC, Vol. 8, No. 4, pp. 431-447, 1989.

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B. Haroun and M. Elmasry, "Architectural Synthesis for DSP Silicon Compiler ", IEEE Trans. CAD/ICAS, pp.431-47, April 1989.

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B. Haroun and M. Elmasry, "Architectural Synthesis for DSP Silicon Compiler," IEEE Trans. on CAD, April 1989.

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B. S. Haroun and M. I. Elmasry, "Architectural synthesis of DSP silicon compiler," IEEE Trans. Computer-Aided Design, vol. 8, no. 4, pp. 431-447, Jun. 1990.

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B. S. Haroun and M. I. Elmasry, "Architectural synthesis of DSP silicon compiler," IEEE TCAD, 8(4):431-447, Jun. 1990.

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