A. Shen, A. Ghosh, S. Devadas, and K. Keutzer. On average power dissipation and random pattern testability of CMOS combinational logic networks. Proc. ACM/IEEE Int. Conf. Computer Aided Design, 1992, pp. 402-407  Home/Search   Document Not in Database   Summary   Related Articles   Check

....on gate inputs occur at di#erent times, the net experiences multiple transitions before settling to its final value. The extra activity due to glitching consumes dynamic power, and previous work has suggested in fact that 20 70 of total power dissipation in ASICs can be due to glitches [13]. An understanding of how switching activity changes when delays are considered is important for several reasons. First, since FPGA power dissipation is dominated by interconnect, the consequences of glitching on total power consumption may be more severe in FPGAs versus ASICs. In addition, due ....

A. Shen and et. al. On average power dissipation and random pattern testability of CMOS combinational logic networks. In IEEE Int. Conf. on Computer-Aided Design, pages 402--407, 1992.

....Equation 3.1 from Section 3.2.1. The use of zero delay model is motivated by very rapid computation of NTC required by the algorithms from Section 3. 4, and by the observation that power dissipation under the zero delay model has a high correlation with power dissipation under the real delay model [176]. Besides, the aim of this chapter is not to give exact values of power dissipation during test application, but to validate the new BPIC test application strategy (Definition 3.5) for power minimisation that equally applies to every delay model. Further, although the power due to glitches is ....

....this section is calculated using the Equation 3.1 from Chapter 3 under the assumption of the zero delay model. The use of the zero delay model is motivated by the observation that power dissipation under the zero delay model has a high correlation with power dissipation under the real delay model [176]. Furthermore, due to elimination of spurious transitions the propagation of hazards and glitches is also eliminated leading to even greater reductions for power dissipation in the case of real delay model, as explained in Section 3.5 from Chapter 3. First column of Table 4.1 gives the number of ....

A. Shen, A. Ghosh, S. Devadas, and K. Keutzer. On average power dissipation and random pattern testability of CMOS combinational logic networks. In Proc. IEEE/ACM International Conference on Computer Aided Design, pages 402--407, 1992.

....such synthesis methods contain two essential components power estimation, and optimization guided by the cost function. Power Estimation Model: In a digital CMOS circuit, dynamic power consumption is the dominant source of power consumption. The amount of energy dissipated in a CMOS circuit [13, 18] is approximately equal to the energy required to charge or discharge the load capacitances at various nodes in the Boolean network. If the circuit is controlled by a global clock, then the estimated average power dissipated is given by (0:5 Theta C l i Theta V dd ) Theta E i =T c (1) E ....

....as well as power dissipation due to glitching are not taken into account in this estimation. In all previous methods, the switching activity is determined either using BDDs [13] or by random pattern simulation using a large number of vectors. The switched capacitance value, as estimated in [18] and [14] is discussed here. Definition 2.1: Given a node n i and fanin node n j , factored load FL(n j ; n i ) is defined as the number of times the variable n j is used (in positive or negative form) in the factored expression of node n i [19] For example, if a node d is expressed as d = ....

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A. Shen, et.al, "On average power dissipation and random pattern testability of CMOS combinational logic networks," ICCAD, 1992.

....important parameter that needs to be optimized along with area and speed. Therefore, extensive research into various aspects of low power system design is presently being conducted. We may classify this research into: 1. power reduction techniques [6, 7, 9] 2. low power synthesis techniques [5, 11,31]; 3. power estimation [20] and 4. fundamental limits on power dissipation [30, 33] While the work presented in this paper focuses on 3. our eventual objective is to enable 2. Power reduction techniques form an integral part of low power VLSI systems design and is presently an active area ....

....with algorithms and architectures and ending with circuits and technological innovations. Existing techniques include those at the algorithmic level (such as reduced complexity algorithms [6] architectural level (such as pipelining [12,25] and parallel pro cessing) logic (logic minimization [31] and precomputation [1] circuit (reduced voltage swing [21] adiabatic logic [3] and technological level [8] It is now well recognized that an astute algorithmic and architectural design can have a large impact on the final power dissipation characteristics of the fabricated VLSI solution. ....

A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," International Conference on Computer-Aided Design, pp. 402-407, November 1992.

....logic state. Although glitches do not affect the final results on synchronous circuits, they can significantly contribute to the growth in the power consumption. Depending on the logic depth, the glitches generated at initial stages may produce an avalanche effect on the circuit activity. In [She92] it is shown that the glitch power component can be up to 20 of the total chip consumption, a percentage that can reach between 30 and 70 for combinatorial circuits [Cha92] As a consequence, a high speed technique like pipelining also become a direct way to reduce power consumption: the ....

A. Shen, A. Gosh, S. Devadas y K. Keutzer, "On average Power Dissipation and Random Pattern Testability of CMOS Combinatorial Logic Networks", Proc. ICCAD-92 Conf, pp.402-407. IEEE Press, 1992.

....with algorithms and architectures and ending with circuits and technological innovations. Existing techniques include those at the algorithmic level (such as reduced complexity algorithms [5] architectural level (such as pipelining [25,32] and parallel processing [33] logic (logic minimization [43] and precomputation [2] circuit (reduced voltage swing [28] adiabatic logic [3,12] and technological level [11] It is now well recognized that an astute algorithmic and architectural design can have a large impact on the final power dissipation characteristics of the fabricated VLSI solution. ....

A. Shen, A. Ghosh, S. Devdas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," IEEE Int. Conf. on Computer-Aided Design, pp. 402-407, 1992.

....adia batic computation [2,12] circuit level) device Oreshold voltage ( reduction [5] device level) and at technological level [11] etc. Estimating the power dissipation (Category 2) for a given architecture is another important problem that has received a lot of attention in recent years [22,23,26,27,33,34]. In [22] an information theoretic approach to power estimation was proposed. In particular, the average value for the number of transitions occurring at the output of a boolean function was obtained as H(Y) 2, where H(Y) is the entropy of the output Y. An empirical measure for the average number ....

A. Shen, A. Ghosh, S. Devdas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," IEEE Int. Conf. on Computer-Aided Design, pp. 402-407, 1992.

....CMOS circuits, information theory, busses I. INTRODUCTION Power dissipation has become a critical VLSI design con cern in recent years [3] and a substantial amount of research is being conducted at the algorithmic [3] architectural (such as pipelining [13] and parallel processing) logic [9, 18] and circuit [4, 8] levels in order to develop power reduction techniques. Most of these efforts focus upon reducing the on chip dynamic power dissipation of CMOS circuits, which at a node is given by, PD iTCLVdf, 1.1) z where T is the transition activity at the node, C is the ca ....

A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, "On aver- age power dissipation and random pattern testability of CMOS combinational logic networks," International Conference on Computer-Aided Design, pp. 402-407, Santa Clara, CA, Novem- ber 8-12 1992.

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A. Shen, S. Devadas, A. Ghosh, and K. Keutzer, "On average power dissipation and random pattern testability of combinational logic circuits," in Proc. Int. Conf. Computer-Aided Design, Nov. 1992, pp. 402--407.

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A. Shen, S. Devadas, A. Ghosh, and K. Keutzer. On Average Power Dissipation and Random Pattern Testability of Combinational Logic Circuits. In Proceedings of the Int'l Conference on ComputerAided Design, pages 402--407, November 1992.

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A. Shen, S. Devadas, A. Ghosh, and K. Keutzer. On Average Power Dissipation and Random Pattern Testability of Combinational Logic Circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 402--407, November 1992.

....levels of the design hierarchy. For instance, algorithmic and architectural transformations can trade off throughput, circuit area, and power dissipation [4] and logic optimization methods have been shown to have a significant impact on the power dissipation of combinational logic circuits [12]. In CMOS circuits, the probabilistic average switching activity of the circuit is a good measure of the average power dissipation of the circuit. Average power dissipation can thus be computed by estimating the average switching activity. Several methods to estimate power dissipation for CMOS ....

....obtain a ROBDD for the g 1 function. A ROBDD can be converted into a multiplexor based network (see [1] or into a sum of products cover. The network or cover can be optimized using standard combinational logic optimization methods that reduce area [2] or those that target low power dissipation [12]. 4.4 Multiple Output Functions In general, we have a multiple output function f 1 ; 1 1 1 ; f m that corresponds to logic block A in Figures 2 and 3. All the procedures described thus far can be generalized to the multiple output case. The functions g 1i and g 2i are obtained using the ....

A. Shen, S. Devadas, A. Ghosh, and K. Keutzer. On Average Power Dissipation and Random Pattern Testability of Combinational Logic Circuits. In Proceedings of the Int'l Conference on Computer-Aided Design, pages 402--407, November 1992.

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A. Shen, A. Ghosh, S. Devadas, and K. Keutzer. On average power dissipation and random pattern testability of CMOS combinational logic networks. Proc. ACM/IEEE Int. Conf. Computer Aided Design, 1992, pp. 402-407

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A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, "On Average Power Dissipation and Random Pattern Testability of CMOS Combinational Logic Networks," Proceedings of the International Conference on Computer-Aided Design, pp. 402-407, November 1992.

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A. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer. On average power dissipation and random pattern testability of CMOS combinational logic networks. In Proceedings of the IEEE International Conference on Computer Aided Design, November 1992. 27

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A. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer. On average power dissipation and random pattern testability of CMOS combinational logic networks. In Proceedings of the IEEE International Conference on Computer Aided Design, November 1992.

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A. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer. On average power dissipation and random pattern testability of CMOS combinational logic networks. In Proceedings of the IEEE International Conference on Computer Aided Design, November 1992.

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A. Shen, A. Ghosh, S. Devdas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," in IEEE Int. Conf. Computer-Aided Design, 1992, pp. 402--407.

No context found.

A. Shen, A. Ghosh, S. Devdas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," in IEEE Int. Conf. Computer-Aided Design, 1992, pp. 402--407.

No context found.

A. Shen, A. Ghosh, S. Devdas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks, " in IEEE Int. Conf. Computer-Aided Design, 1992, pp. 402--407.

No context found.

A. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer. " On average power dissipation and random pattern testability of CMOS combinational logic networks. " In Proceedings of the IEEE International Conference on Computer Aided Design, pages 402-407, November 1992.

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A. Shen, et. al, "On average power dissipation and random pattern testability of CMOS Combinational Logic Networks," IEEE ICCAD, pp. 402-407, 1992. 164

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A.Shen, A.Gosh, S.Devadas, K.Keutzer, On Average Power Dissipation and Random Pattern Testability of CMOS Combinational Logic Networks, Proc. of the ICCAD, pp. 402-407, 1992.

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S. Devadas A. Shen, A. Ghosh and K. Keutzer. On average power dissipation and random pattern testability. In Proc. oflEEE Int. Conf On Computer Aided Design, pages 402 407, November 1992.

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A. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer. " On average power dissipation and random pattern testability of CMOS combinational logic networks. " In Proceedings of the IEEE International Conference on Computer Aided Design, November 1992.

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