T. Callaway and E. Swartzlander, " Optimizing Aritmitic Elements for Signal Processing", VLSI Signal Processing Workshop, pp.91-100, 1992.  Home/Search   Document Not in Database   Summary   Related Articles

....CMOS logic family [5] At a another level, there are various topological choices for implementing a given function. For example, an adder can implemented using ripple carry or carry lookahead approaches. The power trade off between various types of adders and multipliers were investigated in [6] and they concluded that a carry lookahead topology was the best after taking into Previous Work 4 of 27 account the speed capacitance trade off. Optimizing transistor sizing is yet another degree of freedom available in minimizing the energy. To minimize the parasitic capacitances, it is ....

T. Callaway and E. Swartzlander, " Optimizing Aritmitic Elements for Signal Processing", VLSI Signal Processing Workshop, pp.91-100, 1992.

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