K. Yano, et al., "A 3.8ns CMOS 16x16 Multiplier Using Complementary Pass Transistor Logic", IEEE Journal of Solid-State Circuits, pp. 388-395, April 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... that a power consuming transition occurs (the activity factor) In most cases, the voltage swing, V, is the same as the supply voltage, V dd ; however, some logic circuits, such as in single gate pass transistor implementations, the voltage swing on some internal nodes may be slightly less [8]. The second term is due to the direct path short circuit current, I sc , which arises when both the NMOS and PMOS transistors are simultaneously active, conducting current directly from supply to ground [9,10] Finally, leakage current, I leakage , which can arise from substrate injection and ....

....in parasitic capacitance and slower speeds. Circuit Design and Technology Considerations 6 of 18 3.2 Conventional Static vs. Pass gate Logic A more clear situation exists in the use of transfer gates to implement logic functions, as is used in the CPL (Complementary Passgate Logic) family [8,10]. In Figure 1, the schematic of a typical static CMOS logic circuit for a full adder is shown along with a static CPL version [8] The passgate design uses only a single transmission NMOS gate, instead of a full complementary passgate to reduce node capacitance. Passgate logic is attractive as ....

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K. Yano, et al., "A 3.8ns CMOS 16x16 Multiplier Using Complementary Pass Transistor Logic", IEEE Journal of Solid-State Circuits, pp. 388-395, April 1990.

....design. There are a number of options available in choosing and optimizing the basic circuit approach and topology for implementing various logic and arithmetic functions. A pass transistor logic family was found to minimize physical capacitance when compared to a conventional CMOS logic family [5]. At a another level, there are various topological choices for implementing a given function. For example, an adder can implemented using ripple carry or carry lookahead approaches. The power trade off between various types of adders and multipliers were investigated in [6] and they concluded ....

K. Yano, et al., "A 3.8ns CMOS 16x16 Multiplier Using Complementary Pass Transistor Logic", IEEE Journal of Solid-State Circuits, pp. 388-395, April 1990.

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