D. Dahle, "Designing High Performance Systems to Run from 3.3V or Lower Sources," Silicon Valley Personal Computer Conference, pp. 685-691, 1991. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
A Portable Multimedia Terminal for Personal Communications - Sheng (1992) (17 citations) (Correct)
....gate delays becoming relatively independent of the supply voltage. As a result, the supply voltage can be dropped to some extent without a significant reduction in speed. This fact has been exploited to reduce the supply voltage to 3.3V in several emerging low voltage applications. For example, in [10], this approach was found to achieve a 60 reduction in power when compared to a 5V operation. While this approach allows a reduction of voltage to some extent, it is clearly much more advantageous, if possible, to run at much lower supply voltages to minimize the energy per computation. Also, the ....
D.Dahle, "Designing High-Performance Systems to run from 3.3V or lower supplies," in Proc. 1991 Silicon Valley Computer Conference, Santa Clara, CA, 1991.
Low Power CMOS Digital Design - Chandrakasan, Sheng, Brodersen (1995) (280 citations) (Correct)
....dependence. For 0.3 technology, the proposed lower limit on supply voltage (or the critical voltage) was found to be 2.43V. Because of this effect, there is some movement to a 3. 3V industrial voltage standard since at this level of voltage reduction there is not a significant loss of circuit speed[1,25]. This was found to achieve a 60 reduction in power when compared to a 5 volt operation[25] 4.5 Architecture Driven Voltage Scaling The above mentioned technology based approaches are focusing on reducing the voltage while maintaining device speed, and are not attempting to achieve the ....
....was found to be 2.43V. Because of this effect, there is some movement to a 3. 3V industrial voltage standard since at this level of voltage reduction there is not a significant loss of circuit speed[1,25] This was found to achieve a 60 reduction in power when compared to a 5 volt operation[25]. 4.5 Architecture Driven Voltage Scaling The above mentioned technology based approaches are focusing on reducing the voltage while maintaining device speed, and are not attempting to achieve the minimum possible power. As shown in Figures 2 and 4, CMOS logic gates achieve lower power delay ....
D. Dahle, "Designing High Performance Systems to Run from 3.3V or Lower Sources", Silicon Valley Personal Computer Conference, pp. 685-691, 1991.
Optimizing Power Using Transformations - Chandrakasan, Potkonjak, Mehra.. (1995) (97 citations) (Correct)
....independence of delay on supply voltage at high electric fields, the voltage can be dropped to some extent for a velocity saturated device with very little penalty in speed performance. This was found to achieve a 60 reduction in power for a 3. 3V system when compared to a 5 volt operation [4]. 2] presents an architecture based voltage scaling strategy that results in an optimal voltage for power that is much lower (in the 1 1.5V range) than obtained from the technology based scaling. The idea is to maintain throughput at reduced supply voltages through hardware duplication or ....
D. Dahle, "Designing High Performance Systems to Run from 3.3V or Lower Sources", Silicon Valley Personal Computer Conference, pp. 685-691, 1991.
Low Power Architectural Design Methodologies - Landman (1994) (22 citations) (Correct)
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D. Dahle, "Designing High Performance Systems to Run from 3.3V or Lower Sources," Silicon Valley Personal Computer Conference, pp. 685-691, 1991.
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