C. Kern and M. R. Greenstreet, "Formal verification in hardware design: A survey," ACM Transactions on Design Automation of E. Systems, vol. 4, pp. 123--193, Apr. 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....manipulation: image computation union of sets set containment other : We use the following simple example. C G B D E A Figure 1: Simple Combinational Circuit 4. 1 Characteristic representation A detailed description can be found in a number of standard references (e.g. [4, 8, 9]) Let S = B be our state space. As described above to represent using the characteristic method we introduce n variables. Let W be an ordered set of variables. In our world, each variable will corresponds to one of the state components, and so they are often call state variables. To recap, ....

.... encoding of the following set of states: f(a;b;c;0;0;0) a;b;c 2 f0;1g g Applying the next state function we might get (X;X;X; b;a;0) which represents the set f(0;0;0;1;0;0) 0;0;1;1;0;0) 0;1;0;0;0;0) 0;1;1;0;0;0) 1;0;0;1;1;0) g For more detail on this representation see [6, 8, 11]. 5 not canonical don t have nice algorithms for set manipulation to get full benefit of approach, can support limited temporal logics Don t need a monolithic BDD to represent state space or next state function Only as many BDD variables as there are parametric variables largely ....

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C. Kern and M. Greenstreet. Formal verification in hardware design: A survey. ACM Transactions on Design Automation of Electronic Systems, 4(2):123--193, April 1999.

....human life. A major goal of system design is to enable developers to construct systems that operate reliably despite this complexity. One way of achieving this goal is by using formal methods, which are mathematically based languages, techniques, and tools for specifying and verifying such systems [9]. Only recently have we begun to see a more promising picture for the future of formal methods. For hardware verification, industry is adopting techniques like model checking and theorem proving to complement the more traditional one of simulation. Researchers and practitioners are performing ....

C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey", ACM Transactions on Design Automation of E. Systems, Vol. 4, April 1999, pp. 123-193.

....complementing simulation and testing. Formal methods are analytical and mathematical techniques intended to prove formally that the implementation of a system conforms its specification. Formal methods have extensively been used in software development [Gan94] as well as in hardware verification [Ker99]. However, formal verification techniques are not yet commonly used in embedded systems design. 1.2 Problem Formulation The previous section has presented the motivation for our research and pointed out the relevance of the topics addressed in this thesis. The model of computation is the ....

....solution to achieve correct systems. Formal verification is to complement, rather than replace, simulation and testing methods. 6.1. 2 TEMPORAL LOGICS A temporal logic is a logic augmented with temporal modal operators which allow reasoning about how the truth of assertions changes over time [Ker99]. Temporal logics are usually employed to specify desired properties of systems. There are different forms of temporal logics depending on the underlying model of time. In this section, we focus on CTL (Computation Tree Logic) because it is a representative example of temporal logics and it is one ....

C. Kern and M. R. Greenstreet, "Formal Verification in Hardware Design: A Survey," in ACM Trans. on Design Automation of Electronic Systems, vol. 4, pp. 123-193, April 1999.

....simulation has been the main debugging technique. However, due to the increasing complexity of digital systems, it is becoming impossible to simulate large designs adequately. Therefore, there has been a recent surge of interest in alternative complementary techniques, such as formal verification [4]. In formal verification, a mathematical model of the design is compared with a formal specification describing the correctness criteria for the design. The verification is exhaustive: all possible behaviors of the model are considered. In this paper, we describe the functional verification of a ....

C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey," ACM Transactions on Design Automation of E. Systems, Vol. 4, pp. 123-193, April 1999.

....designs as early as possible. Conventionally, simulation has been the main debugging technique. However, due to the increasing complexity of digital systems, it is becoming impossible to simulate large designs adequately. Therefore, there has been a recent surge of interest in formal verification [5]. One very successful formal verification approach is model checking [5] which enables to check a design model against temporal logic properties. Model checking is an automatic technique for verifying finite state reactive systems, such as sequential circuit designs and communication protocols. ....

....debugging technique. However, due to the increasing complexity of digital systems, it is becoming impossible to simulate large designs adequately. Therefore, there has been a recent surge of interest in formal verification [5] One very successful formal verification approach is model checking [5] which enables to check a design model against temporal logic properties. Model checking is an automatic technique for verifying finite state reactive systems, such as sequential circuit designs and communication protocols. Specifications are expressed in a propositional temporal logic, and the ....

[Article contains additional citation context not shown here]

C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey," ACM Transactions on Design Automation of Electronic Systems, Vol. 4, April 1999, pp. 123-193.

....whether the outputs of both models are the same. For a large design, such exhaustive simulation is impossible, so the practical way to do this is using random simulation. However, some special scenarios cannot be detected by random testing. Using equivalence checking based on formal methods [7], such verification is made possible. In fact, if equivalence checking can replace random simulation, such comparison will be more reliable. Because of the above reasons, equivalence checking becomes quite useful in hardware verification. Equivalence checking can be divided into two categories: ....

....[4] can be used to verify the equivalence between two levels of a design without latch mapping. Therefore, it can be applied to verify the equivalence between an RTL design and its behavioral model. But the drawback of sequential equivalence checking is the socalled state space explosion problem [7] so that it is hard to be applied in a large design. To make use of sequential equivalence checking, in [8] we applied modular sequential equivalence checking on the verification of Fairisle ATM (Asynchronous Transfer Mode) switch [9] Modular means to verify the equivalence between submodules of ....

C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey," ACM Transactions on Design Automation of E. Systems, Vol. 4, pp. 123-193, April 1999.

....affects point 7, because many more groups are likely to use a format that their management can comprehend than one that their management sees, often quite literally, as Greek. The above is the case in software development; hardware development using formal methods has seen much greater success [Kern 99] Several possible reasons for the discrepancy exist, but two of them are particularly salient. First, hardware is mass produced and not easily modified. Correcting hardware errors costs much more than patching software, so the cost of implementing formal methods is much easier to justify. ....

Kern, C., and M. Greenstreet. "Formal Verification in Hardware Design: A Survey." ACM Transactions on Design Automation of E. Systems, 4:123-193, April 1999.

....Because exhaustive simulation for complex designs is practically infeasible, simulation provides at best only a probabilistic assurance. Formal verification, in contrast to simulation uses rigorous mathematical reasoning to prove that an implementation meets all or parts of its specification [95]. Testing assures that the function of each manufactured circuit corresponds to the function of the implementation [2, 127] Producing reliable VLSI circuits depends strongly on testing to eliminate various defects caused by the manufacturing process. Basic types of defects in VLSI circuits [138] ....

C. Kern and M.R. Greenstreet. Formal verification in hardware design: A survey. ACM Transactions on Design Automation of Electronic Systems (TODAES), 4(2):123--193, April 1999.

....since hardware design is usually defined as communicating finite state machines (FSMs) In software, on the other hand, it is much harder to extract small state machines needed for model checking. Therefore, in software, model checking as well as other formal methods such as theorem proving [26], are used mainly in the verification of specifications (when the specifications are formally written) While there is a lot of theoretical work, very little is actually applied in the industry. The notable exception is the use of model checking in the testing or verification of protocols, ....

C. Kern and M. R. Greenstreet. Formal verification in hardware design: a survey. ACM Transactions on Design Automation of Electronic Systems, 4(2):123--193, 1999.

....E (F S)# (S F) Therefore, an underlying bipartite graph between storage units and functions can be observed in this model. 2. 2 Formal Verification of Embedded System models Formal verification has been widely applied in both components of an embedded system architecture, i.e. hardware [58] and software [43] as a form of validation which is now rapidly gaining popularity among researchers. The formal verification of an embedded system is normally performed using one out of three techniques: Model Checking [24] Automata Theoretic Approaches [4, 64] and Deductive Methods [31] We ....

Christopher Kern and Mark R. Greenstreet. Formal Verification in Hardware Design: A Survey. ACM Transaction on Design Automation of Embedded Systems, 4(2):1--67, April 1999.

....involves simulation and testing are rapidly becoming infeasible. Formal verification, on the other hand, mathematically checks whether of not the functionality of an embedded system satisfies given properties. This form of validation is increasingly gaining popularity in hardware verification [6] and software development [5] Formal verification techniques based on model checking have been widely used in the verification of finite state concurrent systems. Model checking algorithms [1] decide whether or not a design satisfies some desired properties, which are expressed in a temporal ....

C. Kern and M. R. Greenstreet. Formal Verification in Hardware Design: A Survey. ACM Transaction on Design Automation of Embedded Systems, 4(2):1--67, Apr. 1999.

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C. Kern and M. R. Greenstreet, "Formal verification in hardware design: A survey," ACM Transactions on Design Automation of E. Systems, vol. 4, pp. 123--193, Apr. 1999.

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C. Kern and M. R. Greenstreet, "Formal verification in hardware design: A survey," ACM Transactions on Design Automation of E. Systems, vol. 4, pp. 123--193, Apr. 1999.

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C. Kern and M. R. Greenstreet. Formal verification in hardware design: A survey. ACM Transactions on Design Automation of Electronic Systems, 4(2), April 1999.

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C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey," ACM Trans. on Design Automation of Electronic Systems, Vol. 4, No. 2, Apr. 1999, pp. 123 -- 193.

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C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey," ACM Transactions on Design Automation of Electronic Systems, Vol. 4, pp. 123-193, April 1999.

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C. Kern and M. Greenstreet, "Formal verification in hardware design: A survey," ACM Transactions on Design Automation of Electronic Systems, vol. 4, pp. 123-- 193, Apr. 1999.

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C. Kern and M. R. Greenstreet. Formal Verification in Hardware Design: a Survey, Transactions on Design Automation of Electronic Systems, vol. 4, 1999, pp. 123-193.

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C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey", ACM Trans. on Design Automation of Electronic Systems, Vol. 4, April 1999, pp. 123-193.

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C. Kern and M. R. Greenstreet. Formal verification in hardware design: a survey. Transactions on Design Automation of Electronic Systems, 4:123--193, 1999.

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C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey," ACM Transactions on Design Automation of E. Systems, Vol. 4, pp. 123-193, April 1999.

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C. Kern and M.Greenstreet. Formal Verification in Hardware Design: A Survey. ACM Transactions, 4(2):123--193, April 1999.

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C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey," ACM Transactions on Design Automation of E. Systems, Vol. 4, pp. 123-193, April 1999.

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C. Kern, and M. R. Greenstreat, "Formal verification in Hardware Design: A Survey", ACM transactions on Design Automation of Electronic Systems, Vol. 4 No. 2, April 1999.

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C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey," ACM Transactions on Design Automation of Electronic Systems, Vol. 4, April 1999, pp. 123193.

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