F. J. R. Clement, E. Zysman M. Kayal, and M. Declercq. Layin: Toward a global solution for parasitic coupling modeling and visualization. In Proc. IEEE Custom Integrated Circuit Conference, pages 537--540, May 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....mixed signal design, the noise injected into the substrate by the digital part can seriously influence the functionality of the analog part. Thus, accurately modeling the behaviour of the substrate as a noisepropagator is becoming ever more important in the field of layout to circuit extraction [1, 2, 3, 4, 5, 6, 7, 8]. Basically, there are two principal ways of obtaining such a model: the Finite Element Method (FEM; applied in e.g. 6] and the Boundary Element Method (BEM; described in e.g. 5] The FEM, which makes a full, in depth 3D discretization of the substrate, is usually slow, but very versatile and ....

F.J.R. Clement, E. Zysman, M. Kayal, and M. Declercq, "LAYIN: Toward a global solution for parasitic coupling modeling and visualization," in Proc. IEEE Custom Integrated Circuits Conference, pp. 537 -- 540, May 1994.

....design practices that allowed them to ignore substrate coupling problems are being abandoned. Not only is this making substrate coupling problems more commonplace, but the ones that do occur are harder to analyze. For this reason, there is renewed interest in analyzing substrate coupling[1, 2, 3, 4, 5]. Because of the complexity of the substrate interactions, it is important to find robust and effective numerical techniques for substrate parasitic extraction and consequent simulation of substrate effects on circuit performance. Compared to other parasitic extraction and analysis problems, such ....

F. J. R. Clement, E. Zysman, M. Kayal, and M. Declercq, "LAYIN: Toward a global solution for parasitic coupling modeling and visualization," in Proc. IEEE Custom Integrated Circuit Conference, May 1994, pp. 537--540.

....CMOS circuits this noise is caused by three mechanisms: coupling from the digital power supply, coupling from switching drain source nodes and impact ionization. Noise on the digital power supply is caused by voltage fluctuations due to resistance and inductance in the power supply connections [5] [7]. Since the digital ground is connected to the substrate in every standard CMOS gate, the total resistance between digital ground and substrate is very low (less than 1 #) So all noise present on the digital ground is directly coupled to the substrate. This noise coupling mechanism is often the ....

....noise in cmos integrated circuits, Analog Integrated Circuits and Signal Processing, vol. 14, pp. 113 129, 1997. 6] T. Gabara, Reduced ground bounce and improved latch up suppression through substrate conduction, IEEE J. Solid State Circuits, vol. 23, no. 5, pp. 1224 1232, Oct. 1988. [7] R. Senthinathan and J. L. Prince, Simultaneous switching ground noise calculation for packaged cmos devices, IEEE J. Solid State Circuits, vol. 26, no. 11, pp. 1724 1728, Nov. 1991. 8] J. Briaire and K. S. Krisch, Substrate injection and crosstalk in cmos circuits, in Proc. 1999 IEEE ....

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F.J.R. Clement, E. Zysman, M. Kayal, and M. Declercq, "LAYIN : Toward a Global Solution for Parasitic Coupling Modeling and Visualization", in CICC'94 Proc. Custom Integrated Circuits Conference, page 537 -- 540, San Diego -- California, May 1994.

....of advanced miniaturization has fundamentally revolutionized the field. Two main approaches have emerged. The first, known as macro modeling, consists of generating compact analytical representations of substrate induced parasitics [2, 3, 4] The second approach is based on a fully numerical [5, 6, 7] or semi analytical [8, 9, 10, 11] solution of the ordinary differential equations (ODEs) underlying substrate transport. Characterizing substrate transport mechanisms requires the computation of the electric potential Phi(x; y; z; t) at any bulk point r = x; y; z) in the vicinity of the ....

....that the faces in each box are equipotential. By setting all the nodes associated with a given contact to 1 Volt and by measuring the current flowing out of each other contact, one can compute the resistance between each contact pairs. Techniques based on this concept are currently used in LAYIN [5]. The resulting system of simultaneous equations is diagonally dominant and sparse, since only seven elements in each row are non zero. Hence, standard techniques for the solution of sparse linear systems can be applied [12] The most commonly used methods in substrate related literature are (1) ....

F. J. R. Clement, E. Zysman M. Kayal and M. Declercq, "LAYIN: Toward a Global Solution for Parasitic Coupling Modeling and Visualization ", in Proc. IEEE Custom Integrated Circuit Conference, pp. 537--540, May 1994.

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F. J. R. Clement, E. Zysman M. Kayal, and M. Declercq. Layin: Toward a global solution for parasitic coupling modeling and visualization. In Proc. IEEE Custom Integrated Circuit Conference, pages 537--540, May 1994.

No context found.

F. J. R. Clement, E. Zysman M. Kayal, and M. Declercq. Layin: Toward a global solution for parasitic coupling modeling and visualization. In Proc. IEEE Custom Integrated Circuit Conference, pages 537--540, May 1994.

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