L. Thiele. On the analysis and optimization of selftimed processor arrays. INTEGRATION, 12(2):167-- 187, Dec. 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....and all of the odd indexed stages become enabled. One more time unit later, the odd indexed stages fire, and the even indexed stages become enabled again. Thus, each stage has a cycle time of two time units. The performance of self timed rings have been studied in various contexts. For example, [14] analyzed various, regular arrays of self timed processors, assuming each processor has a fixed time for each operation. Self timed rings with exponentially distributed processing times were analyzed in [4] and self timed meshes in [11] Xie and Beerel have developed tools that analyze general ....

L. Thiele. On the analysis and optimization of selftimed processor arrays. INTEGRATION, 12(2):167-- 187, Dec. 1991.

....uniformlyburst . Sampling the output of one stage in a ring. Figure 1.1: Burst and Uniformly Spaced Events 1.1.1 Self txF4 Rings Self timed rings are ubiquitous in self timed designs (e.g. W0zk , SS93] and their performance has been studied in many contexts. For example, Thi91] analyzed throughput assuming each stage has a fixed time for each operation. Self timed rings with exponentially distributed processing times were analyzed in [GS90] Xie and Beerel have developed tools that analyze general networks of self timed processors for general probabilistic models ....

Lothar Thiele. On the analysis and optimization of self-timed processor arrays. INTEGRATION, 12(2):167--187, December 1991.

....focus on the timing of operations in the ring and do not give further consideration to any data values that may be conveyed with the tokens or bubbles. Self timed rings are ubiquitous in self timed designs (e.g. Wil91,SS93] and their performance has been studied in many contexts. For example, Thi91] an alyzed throughput assuming each stage has a xed time for each operation. Self timed rings with exponentially distributed processing times were analyzed in [GS90] Xie and Beerel have developed tools that analyze general networks of self timed processors for general probabilistic models ....

Lothar Thiele. On the analysis and optimization of self-timed processor arrays. INTEGRATION, 12(2):167-187, December 1991.

....rings of Williams [27] and Spars and Staunstrup [22] and the Amulet2e [5] are all arbiterfree designs. Likewise, much of the performance analysis that has been published focuses on designs without arbiters: for example, the analysis of self timed pipelines in [8] and [28] or that of meshes in [25] and [20] Burns analysis technique for the Caltech processor [3] considered probabilistic instruction mixes but was still restricted to an arbiter free design style. The recent work of Xie and Beerel [29, 30] based on Markov chains provides a framework in which the impact of arbiter design on ....

L. Thiele. On the analysis and optimization of selftimed processor arrays. INTEGRATION, 12(2):167-- 187, Dec. 1991.

....self timed designs have been proposed as a solution to the clock skew problem [Sei79, FK85, MBM88] there has be a paucity of analysis to support claims that self timed processors scale well. Chapter 2 analyzes the performance of self timed pipelines. Unlike other studies [Bur91, Wil91, Thi91a] that consider specific, small pipelines, and fixed delays, the analysis in chapter 2 addresses issues of scalability by considering asymptotic performance and issues of uncertainity by employing 5 probabilistic delay models. We show that self timed processors can achieve linear asymptotic ....

....problems of clock skew, some designers [MB59, Sei79, Sin81, Udd84, MFR85, MBM88, Mar90] have promoted purely self timed designs. Many analyses have appeared recently that address the performance of self timed processors assuming deterministic delays of logic elements and wiring [Bur91, Wil91, Thi91a] Each of these shows that an analysis of parallel program performance originally by Reiter [Rei68] can be applied to self timed circuits. Each of these studies assumes fixed times for each circuit element to perform each operation, variations in these delays are neglected. As it is the ....

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Lothar Thiele. On the analysis and optimization of selftimed processor arrays. INTEGRATION, 12(2):167--187, December 1991.

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