Y. Zhang. "Hardware for Speculative Parallelization in DSM Multiprocessors. " Ph.D. Thesis, University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, May 1999.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....tailored at being integrated into large system configurations. Only [17] is designed for multichip configurations. One possible way to address this limitation is to extend a scalable cache coherence protocol to support speculative parallelization. There have been two proposals in this direction [17, 18, 22, 23, 24]. Both schemes extend an invalidation based cache coherence protocol. They both yield a flat view of their speculation threads. Neither of these proposals is fleshed out enough to show how, if speculative CMPs were used as building blocks, it would reconcile its single layer protocol with many of ....

....of such a speculative CMP. We borrow the MDT concept in our study and use this speculative CMP as the building block. Our scalable scheme, however, is not dependent on the MDT based CMP and could easily accommodate the other speculative CMP proposals mentioned above. The work in [17, 18] and in [22, 23, 24] presents extensions to a cache coherence protocol to accommodate speculation in scalable systems. Both designs yield a flat view of their speculation threads. Neither of these proposals is fleshed out enough to show how, if speculative CMPs were used as building blocks, it would reconcile its ....

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Y. Zhang. "Hardware for Speculative Parallelization in DSM Multiprocessors. " Ph.D. Thesis, University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, May 1999.

....subsets called wavefronts. Each wavefront is then executed in parallel by the executor, with synchronization separating the wavefronts. In general, however, the inspector may be computationally expensive and have side e ects. We propose a new framework for speculative parallelization in hardware [17, 18, 19]. The scheme is based on a softwarebased run time parallelization scheme that we proposed earlier [13] The idea is to execute the code (loops) speculatively in parallel. As parallel execution proceeds, extra hardware added to the directory based cache coherence of the DSM machine detects if there ....

....the second scheme is targeted to loops that have a modest number of cross iteration dependences. 2 Base Scheme for Speculative Parallelization In this scheme, the safe state to which we will roll back in software in case of a dependence violation, is established at the beginning of the loop [17, 18, 19]. This scheme can be eshed out into di erent hardware algorithms with di erent cost and performance. We envision the DSM machine to support a few such algorithms mapped to the same hardware, and the compiler to select the algorithm on an array by array basis. First, there are the privatization ....

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Y. Zhang. Hardware for Speculative Parallelization in DSM Multiprocessors. Ph.D. Thesis, University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, expected March 1999.

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