M. Tremblay, B. Joy, and K. Shin. A three dimensional register file for superscalar processors. In 28th Hawaii International Conference on System Sciences, pages 191-- 201, January 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....high performance microprocessor requires a register file with many read and write ports. This highly multiported structure becomes challenging to design because the area of a register file increases quadratically and the latency increases approximately linearly as the number of ports grows [6][7][8] Conventional register files in RISC style microprocessors have two register read ports and one write port per issue slot. Even though this 2X read port configuration guarantees register accesses for all types of instructions, it 1. The wakeup bus length and the number of tag comparators of ....

M. Tremblay, B. Joy and K. Shin, A three dimensional register file for superscalarprocessors, in Proc. of 28th Hawaii International Conference on System Sciences, pp. 191-201, 1995.

....visible to software. The SPARC architecture [21] has overlapping register windows where software explicity switches between sets of registers. In order superscalar implementations of the UltraSPARC exploit the fact that only one register window is visible to implement a dense multiported structure [18]. Clustered VLIW machines make the presence of multiple register file banks visible to software, and the compiler is responsible for mapping instructions to clusters [10] Vector machines have also long been designed with interleaved register file banks that exploit the regular access patterns of ....

M. Tremblay, B. Joy, and K. Shin. A three dimensional register file for superscalar processors. In HICSS,Jan- uary 1995.

....file. 4.2. 1 Methodology Silicon area estimation The silicon footprint of a multiported register file is dominated by the area devoted to memory cells [21] When the number of ports is high, the size of a multiported memory cell is approximately a quadratic function of its number of access ports [19]. For a conventional multiported memory cell featuring ports and ports, bitlines, wordline wires, bitlines and wordline wires must cross the cell [21] being the width of each wire (i.e. the width of the wire itself plus the distance with the neighbor wire) the area devoted ....

Marc Tremblay, Bill Joy, and Ken Shin. A three dimensional register file for superscalar processors. In Proceedings of the 28th Annual Hawaii International Conference on System Sciences, Jan 1995.

....design, since the additional indexing must fit into the clock cycle. We are confident that it is possible to build such a RegMap with the same timing performance as the original RegMap for a monopath architecture. One promising direction for implementing the RegMap is the use of a 3D register file [19]. However, in Sec. 5.3.4 we also provide results for the case where an additional cycle for this operation might become necessary. 3.2.6 Context Management The front end also performs CTX management operations. This involves CTX tag management, as described in Sec. 3.2.2, as well as CTX fetch ....

M. Tremblay, B. Joy, and K. Shin. A Three Dimensional Register File for Superscalar Processors. In 28th Hawaii Intl. Conf. on System Sciences, pages 191--201, January 1995.

....regfile size, with 80 physical registers. The average energy dissipation per regfile access increases with the 66 size of regfile. Also, multiple issue high performance microprocessors require regfiles with many read and write ports. The silicon area grows quadratically in the number of ports [16]. Therefore, one can expect that these microprocessors regfiles consume a higher percentage of total energy than in single issue microprocessors. The potential energy saving of the five regfile energy reduction techniques proposed for the single issue microprocessors in this thesis should be ....

M. Tremblay, B. Joy, and K. Shin. A three dimensional register file for superscalar processors. In Proceedings of the 28th Annual Hawaii International Conference on System Sciences, pages 191--201, January 1995.

....since the additional indexing must fit into the clock cycle. We are confident though, that it is possible to build such a RegMap with the same timing performance as the original RegMap for a monopath architecture. One promising direction for implementing the RegMap is the use of a 3D register file [19]. However, in Sec. 5.3.4 we also provide results for the case where an additional cycle for this operation might become necessary. branch resolution bus branch commit bus CTX tag decode management to fetch decode CTX Table status PC invalidation to fetch T X T N confidence branch from ....

M. Tremblay, B. Joy, and K. Shin. A Three Dimensional Register File for Superscalar Processors. In 28th Hawaii Intl. Conf. on System Sciences, pages 191--201, January 1995.

....only 7 words, while the largest frame was 282 words. Floating point programs produced similar numbers also. The results suggest that if a separate cache is used to hold the local variables, it need not be large to obtain a high hit rate. In fact, this has been the motivation for some previous work [8, 12, 26, 29]. The high frequency of local variable accesses and their strong locality motivate us to consider decoupling and servicing the local variable accesses separately. Moreover, identifying local variables in the stack frames is relatively easy for hardware or compiler. 2.2.2 Architectural support To ....

....has considered separating local variable accesses to relieve the data cache bandwidth in the context of a wide issue superscalar processor. Among current microprocessors, Sun UltraSparc employs a special register file structure called register window to reduce the cost of a procedure call return [29]. Chow and Hennessy [7] categorize memory traffic into five types of references after register allocation unallocated references, global scalars, save restore memory references, a required stack reference, and a computed reference. Register allocation techniques with various heuristics [4, 2, ....

M. Tremblay, B. Joy, and K. Shin. "A Three Dimensional Register File for Superscalar Processors," Proc. of the 28th Annual Hawaii Int'l Conf. on Systems Sciences, IEEE CS Press, 1995.

....and Dally s [17] named state register file caches register values by dynamically mapping active registers to a small, fast set of registers, while backing the full register name space in memory. To reduce the required chip area in processors with register windows, Sun designed 3 D register files [22]. Because only one register window can be active at any time, the density of the register file can be increased by overlaying multiple register cells so that they share wires. Several papers have investigated register lifetimes and other register issues. Farkas, et al. 6] 264 regs 288 regs 320 ....

M. Tremblay, B. Joy, and K. Shin. A three dimensional register file for superscalar processors. In Hawaii International Conference on System Sciences, pages 191--201, January 1995. Page 17

....and Dally s [17] named state register file caches register values by dynamically mapping active registers to a small, fast set of registers, while backing the full register name space in memory. To reduce the required chip area in processors with register windows, Sun designed 3 D register files [22]. Because only one register window can be active at any time, the density of the register file can be increased by overlaying multiple register cells so that they share wires. Several papers have investigated register lifetimes and other register issues. Farkas, et al. 6] compared the register ....

M. Tremblay, B. Joy, and K. Shin. A three dimensional register file for superscalar processors. In Hawaii International Conference on System Sciences, pages 191--201, January 1995.

....size is 282 words. The result suggests that if a separate cache is used to hold the local variables, it need not be large to obtain a high hit rate. The cache size to capture ten outstanding function frames is only 70 words on average. In fact, this has been the motivation for some previous work [6, 10, 24, 27]. The high frequency of local variable accesses and their spatial locality motivate us to consider decoupling and servicing the local variable accesses separately. Moreover, identifying local variables in the stack frames is relatively easy for a compiler. 2.2.2 Architectural support To ....

....has considered separating local variable accesses to relieve the data cache bandwidth in the context of a wide issue superscalar processor. Among current microprocessors, Sun UltraSparc employs a special register file structure called register window to reduce the cost of a procedure call return [27]. Chow and Hennessy [5] categorize memory traffic into five types of references after register allocation unallocated references, global scalars, save restore memory references, a required stack reference, and a computed reference. Register allocation techniques with various heuristics [4, 2, ....

M. Tremblay, B. Joy, and K. Shin. "A Three Dimensional Register File for Superscalar Processors, " Proc. of the 28th Annual Hawaii Int'l Conf. on Systems Sciences, IEEE CS Press, 1995.

....work was supported in part by the National Science Foundation under Grant No.MIP 95 03682. storage size and the number of ports of on chip memories will grow in the future. The silicon area of a multiported memory, built using conventional approaches, grows quadratically in the number of ports [25]. Therefore, taking into account growth both in storage size and the number of ports, we can expect that the power portion of multiported on chip memories will grow rapidly in the future. A lot of work has been done in estimating the minimum cycle time for on chip memories. In this work we ....

....approach to the RF design. The conventional multiported memory cell for RF, Figure 2, typically uses two bit lines per write port and one bit line per read port, as well as one word line per every port to control the connection of the cell to the bit lines of the corresponding port [21] [25], 16] 19] Thus, there are N read Nwrite word lines for every row in the array, and N read 2Nwrite bit lines. Multiple word lines can go high at the same time in case of simultaneous access through several ports to the same cell. Therefore the cell must be capable of driving significant ....

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M. Tremblay, B. Joy and K. Shin, "A Three Dimensional Register File For Superscalar Processors." In: Proceedings of the 28th Annual Hawaii International Conference on System Sciences. pp. 191--201, January 1995. -- 15 --

....and Dally s [19] named state register file caches register values by dynamically mapping active registers to a small, fast set of registers, while backing the full register name space in memory. To reduce the required chip area in processors with register windows, Sun designed 3 D register files [24]. Because only one register window can be active at any time, the density of the register file can be increased by overlaying multiple register cells so that they share wires. Several papers have investigated register lifetimes and other register issues. Farkas, et al. 6] compared the register ....

M. Tremblay, B. Joy, and K. Shin. A three dimensional register file for superscalar processors. In 28th Hawaii International Conference on System Sciences, pages 191--201, January 1995.

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M. Tremblay, B. Joy, and K. Shin. A three dimensional register file for superscalar processors. In 28th Hawaii International Conference on System Sciences, pages 191-- 201, January 1995.

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