L. Gwennap, MAJC Gives VLIW a New Twist, Microprocessor Report 13 (12) (1999) 12-15.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....workload and if the time necessary for switching of threads is very small. In consequence, recent announcements of high performance processors by industry concern a 4 threaded Alpha processor of DEC Compaq [9] and Sun s MAJC 5200 processor, which feature two 4 threaded processors on a single die [10]. Both processors are designed as high performance processors and will not be suitable for low cost embedded systems. However, the multithreaded MediaProcessor of MicroUnity [11] is specialized for multimedia appliances and the recent multithreaded Network Communication Processor of XStream Logic ....

L. Gwennap. MAJC Gives VLIW a New Twist. Microprocessor Report, 13(12):12--15, September 1999.

....or instruction memory already exist in microprocessors. For example, the MIPS R10000 cache instruction can read and write data, tags, and control bits in the instruction cache. A further example is the MAJC architecture which specifies a special instruction for writing into instruction memory [Gwennap99]. These mechanisms have uses beyond just code compression. Jacob et al. propose using such features to replace hardware managed address translation performed by the translation lookaside buffer with software managed address translation [Jacob97] Jacob further suggests using software managed ....

L. Gwennap, "MAJC Gives VLIW a New Twist", Microprocessor Report, 13(12), pp. 13-15:22, Sept. 13, 1999.

....link, reducing the area overhead for a 64 way memoizing cache by 6 . This optimization also reduces the energy overhead that arises from reading out 7 extra state in the cache, which was shown to have a large effect on the energy performance of the way memoizing cache. As has been proposed in [7], it is possible to precompute the low order bits of branch destinations and store them in the instruction cache, instead of the original PC relative offset. As a result, low order bits do not have to be recalculated every time the branch is executed, thus saving power. Combined with ....

L. Gwennap. MAJC gives VLIW a new twist. Microprocessor Report, 13(12):12--15,22, September 1999.

.... superscalar processors for multi programmed or multithreaded workloads (see e.g. 14 ] In consequence, recent announcements by industry concern a 4 threaded 8 issue SMT Alpha processor of DEC Compaq [5] and the MAJC 5200 processor of Sun, which features two 4 threaded processors on a single die [6]. It is unfair, however, to compare the performances of multithreaded processor models with single threaded processor models applying otherwise the same configuration parameters. The resources of the single threaded model should be adjusted such that the same chip space or the same transistor ....

Gwennap, L.: MAJC Gives VLIW a New Twist. Microprocessor Report, Sept. 13, 1999.

....as workload and if the time necessary for switching of threads is very small. In consequence, recent announcements of high performance processors by industry concern a 4 threaded Alpha processor of DEC Compaq [1] and Sun s MAJC 5200 processor which features two 4threaded processors on a single die [2]. Both processors are designed as high performance processors and will not be suitable for low cost embedded systems. Contemporary microprocessors and microcontrollers activate Interrupt Service Routines (ISRs) for event handling. Events of different priorities are handled by ISRs with ....

L. Gwennap. MAJC Gives VLIW a New Twist. Microprocessor Report, Vol 13, No. 12, pp. 12--15, September, 1999.

....as workload and if the time necessary for switching of threads is very small. In consequence, recent announcements of high performance processors by industry concern a 4 threaded Alpha processor of DEC Compaq [1] and Sun s MAJC 5200 processor which features two 4threaded processors on a single die [2]. Both processors are designed as high performance processors and will not be suitable for low cost embedded systems. Our Komodo project [3] explores the suitability of multithreading techniques in embedded real time systems. We propose multithreading as an event handling mechanism that allows ....

L. Gwennap. MAJC Gives VLIW a New Twist. Microprocessor Report, Vol 13, No. 12, pp. 12--15, September, 1999.

....will be an SMT processor [5] We expect that the JVM BLP system would also perform well on other multi threaded systems that have the ability to concurrently execute multiple threads. For example, JVM BLP can also take advantage of chip multiprocessing [14] that Sun s MAJC processor architecture [8] and IBM s Power4 Processor [6] support. Chip multiprocessing runs threads on separate processor cores that share the same die and usually share the same second level cache. The threads are therefore not as closely coupled as in an SMT processor, and the multi threading and synchronization ....

L. Gwennap. MAJC gives VLIW a new twist. Microprocessor Report, Sep. 13 1999.

....performance by masking latencies of instructions of the presently scheduled thread by instructions of other threads. Thus the throughput of a multiprogramming workload is increased leading to very powerful techniques that appear in next generation s multiple issue microprocessors (see Sun s MAJC [4], and DEC Compaq s EV8 Architecture [5] However, to date multithreading has never been applied for event handling by taking advantage of its fast con text switching ability. The basic multithreading techniques that are appropriate for microcontrollers with a single issue RISC processor kernel ....

L. Gwennap. MAJC Gives VLIW a New Twist. Microprocessor Report, Vol 13, No. 12, pp. 12--15, September, 1999.

....IPC increase over single threaded superscalar processors due to SMT s latency tolerance. In consequence, recent announcements by industry concern a 4 threaded SMT Alpha processor of DEC Compaq [10] and the MAJC 5200 processor of Sun which features two 4 threaded processors on a single die [11]. Our goal is to evaluate simultaneous mult it hreading with a mult imedia workload. We reported on optimizations for a maximum processor model with an abundance of resources in [12] and on a more realistic processor model in [13] Other approaches [14, 15] looked at the application of the SMT ....

Gwennap, L.: MAJC Gives VLIW a New Twist. Microprocessor Report, Sept. 13, 1999.

....performance by masking latencies of instructions of the presently scheduled thread by instructions of other threads. Thus the throughput of a multiprogramming workload is increased leading to very powerful techniques that appear in next generation s multiple issue microprocessors (see Sun s MAJC [4], and DEC Compaq s EV8 Architecture [5] However, to date multithreading has never been applied for event handling by taking advantage of its fast context switching ability. The basic multithreading techniques that are appropriate for microcontrollers with a single issue RISC processor kernel ....

L. Gwennap. MAJC Gives VLIW a New Twist. Microprocessor Report, Vol 13, No. 12, pp. 12--15, September, 1999.

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L. Gwennap, MAJC Gives VLIW a New Twist, Microprocessor Report 13 (12) (1999) 12-15.

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