Philips Electronics, TriMedia Product Group. TM1000 Preliminary Data Book, 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the head of the queue. When all queues are emptied, emb fence returns control to the caller. 3. Implementation We implemented ENSEMBLE (and the Spar Java compiler) on a heterogeneous multi processor system consisting of one host CPU (AMD Athlon [1] and three multimedia DSPs (Philips TriMedia [11]) connected by a PCI bus. The Spar Java compiler generates C code, which is then compiled for the Athlon and cross compiled for the TriMedia. The Athlon executable downloads the TriMedia code on the three embedded processors and initiates execution. 5 The three TriMedia processors perform the ....

Philips Electronics, TriMedia Product Group. TM1000 Preliminary Data Book, 1997.

....effect on earlier research. Architecture Type Architecture Family Register Configuration Embedded SHARC ADSP 2106x [AD96] 16 primary; 16 alternate; 40 bits wide TI TMS320C6x [TI97] 2 files of 16 registers; 32 bits wide; 1 Mbit on chip program cache data memory Philips TriMedia TM1000 [TM1K] 128 registers; 32 bits each Siemens TriCore [Siem97] 16 address; 16 data; 32 bits wide Patriot PSC1000 [PTSC] 52 general purpose registers; 32 bits wide Workstation Intel IA32 [Inte96] 8 int; 8 float in a stack; 32 bits wide Transmeta Crusoe TM3120, TM5400 [Klai00] 64 int; 32 bits wide ....

Philips Electronics. TM1000 Preliminary Data Book. TriMedia Product Group, 8111 E. Arques Avenue, Sunnyvalue, CA 94088. 1997.

....the head of the queue. When all queues are emptied, emb fence returns control to the caller. 3. IMPLEMENTATION We implemented ensemble (and the Spar Java compiler) on a heterogeneous multi processor system consisting of one host CPU (AMD Athlon [1] and three multimedia DSPs (Philips TriMedia [12]) connected by a PCI bus. The Spar Java compiler generates C code, which is then compiled for the Athlon and cross compiled for the TriMedia. The Athlon executable downloads the TriMedia code on the three embedded processors and initiates execution. The three TriMedia processors perform the ....

Philips Electronics, TriMedia Product Group. TM1000 Preliminary Data Book, 1997.

....in this paper. The first is traditional Architecture Type Architecture Family Register Configuration Embedded SHARC ADSP 2106x [25] 16 primary; 16 alternate; 40 bits wide TI TMS320C6x [28] 2 files of 16 registers; 32 bits wide; 1 Mbit on chip program cache data memory Philips TriMedia TM1000 [32] 128 registers; 32 bits each Siemens TriCore [29] 16 address; 16 data; 32 bits wide Patriot PSC1000 [33] 52 general purpose registers; 32 bits wide Workstation Intel IA32 [30] 8 int; 8 float in a stack; 32 bits wide Transmeta Crusoe TM3120, TM5400 [34] 64 int; 32 bits wide Intel IA64 [31] ....

Philips Electronics. TM1000 Preliminary Data Book. TriMedia Product Group, 8111 E. Arques Avenue, Sunnyvalue, CA 94088. 1997.

....(DSPCPU) and a range of media speci c units: video and audio interfaces and coprocessors, memory interface, PCI bus interface, etc. The di erent units are interconnected through a highbandwidth internal bus. The processor has a 32 kilobyte 8 way instruction cache and a 16 kilobyte 8 way data cache[21]. The 32 bit DSPCPU consists of 27 functional units, and 128 generalpurpose registers. The instruction set uses a VLIW [12] architecture and allows up to ve operations to be issued in each clock cycle. An instruction can also be guarded by a condition register. 4.2 Used transformations ....

Philips. TM-1 Preliminary Data Book, jan 1996.

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