T. Sherwood, B. Calder, and J. Emer. Reducing Cache Misses using Hardware and Software Page Placement. In Proc. of the 1999. Home/Search Document Details and Download
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Memory Resource Management in VMware ESX Server - Waldspurger (2002) (16 citations) (Correct)
....9] In general, page remapping is a well known approach that is commonly used to change virtual to physical mappings in systems that do not have an extra level of virtualized physical addressing. For example, remapping and page coloring have been used to improve cache performance and isolation [17, 19, 21]. The ESX Server mechanism for working set estimation is related to earlier uses of page faults to maintain per page reference bits in software on architectures lacking direct hardware support [2] However, we combine this technique with a unique statistical sampling approach. Instead of tracking ....
Timothy Sherwood, Brad Calder and Joel S. Emer. "Reducing Cache Misses Using Hardware and Software Page Placement," Proc. International Conference on Supercomputing, June 1999.
A Selective Hardware/Compiler Approach for Improving.. - Memik, Kandemir.. (Correct)
.... techniques proposed are victim caches [18] column associative caches [1] hardware prefetching [3, 32, 22] cache bypassing using memory address table (MAT) 16, 17] dual split caches [26, 13] skewed associative caches [37, 4] multi port caches [27, 28] and careful page placement techniques [38]. 1.2 Software Techniques In the software area, there is a considerable work on compiler directed data locality optimizations. In particular, loop restructuring techniques are widely used in optimizing compilers [47] Within this context, loop level transformations such as loop interchange [45] ....
T. Sherwood, B. Calder, and J. Emer. Reducing cache misses using hardware and software page placement. In Proc. the ACM International Conference on Supercomputing (ICS'99), Rhodes, Greece, June 1999.
On Null Spaces and their Application to Model.. - Vandierendonck, De.. (2002) (Correct)
....was done in [VDB02] 2. 1 Randomisation Functions Several researchers have advocated the use of randomisation over bit selection for index functions, both for interleaving [Rau91, FJL85, VLL 89, VLA92, HIL89, RH90, Soh93, Soh88] and for set index functions [TGG97, GVTP97, TG99, GVTP96, SSS93, SCE99, Sez93, BS95, AP93, AHH88] Randomisation functions have the bene t that they can avoid stereotypical bad behaviour that occurs when the distance between addresses is a power of 2. Randomisation functions can be constructed that provide con ict free mapping for the frequently used distances ....
T. Sherwood, B. Calder, and J. Emer. Reducing cache misses using hardware and software page placement. In International Conference on Supercomputing, pages 155-164, 1999.
Microarchitectural and Compile-Time Optimizations for.. - Kalamatianos (2000) (1 citation) (Correct)
....research. We can fundamentally separate code reordering approaches into three groups based on the granularity of the code module under consideration: page, procedure and basic block. Traditionally page repositioning algorithms have targeted the improvement of the average memory access time [62, 63, 64, 65]. Some of them require some form of operating system support. Procedure reordering also focuses on improving the memory access time [52, 54, 55, 66, 67, 68] Basic block techniques can be roughly characterized as intra or interprocedural. Intraprocedural rearrange blocks strictly within the ....
....I TLB misses. Even in gcc, the increase was substantial when procedure reordering was used alone. If we observe Table 2.4, we see that the largest memory gaps were created for gcc. A solution to this problem would be to adjust the memory placement algorithm to perform software based page coloring [65]. Instead of trying to place procedures as close to each other as possible, we could place them in pages that correspond to different I TLB entries. The remaining benchmarks show a significant decrease in I TLB misses since popular procedure mapping improved page placement. The number of allocated ....
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T. Sherwood, B. Calder, and J. Emer. Reducing Cache Misses using Hardware and Software Page Placement. In Proceedings of the International Conference on Supercomputing, June 1999.
Dynamic Cache Partitioning via Columnization - Chiou, Rudolph, Devadas, Ang (2000) (4 citations) (Correct)
....or in the TLB that is then converted to the respective page numbers can simplify remapping. Separate cache addresses are needed at each level of the memory hierarchy that supports retargetting. An identical mechanism to reduce conflicts in direct mapped caches has been independently proposed [28]. Using retargetting, our 8 continuous pages example can be mapped to 0, 1, 2, 3, 4, 5, 6, and 7 cache pages by mapping the 8 pages across all four cache pages in column 0, 2 cache pages in column 1 and 1 cache page in column 2 (Figure 3) To map to 1 page, set the tint to bit vector to replace ....
....cache pollution causes, but requires additional support, in the form of read buffers, to exploit spatial locality. In addition, they generally do not deal well with data that should be cached, but that should take less space that a standard replacement algorithm allocates 16 it. Page coloring[3, 28] uses selective mappings of virtual to physical addresses in order to reduce conflicts within a direct mapped cache. It can make a direct mapped cache perform like a low way set associative cache. Page coloring, however, cannot map a contiguous region of address space to a smaller region of cache ....
T. Sherwood, B. Calder, and J. Emer. Reducing Cache Misses Using Hardware and Software Page Placement. In Proceedings of the International Conference on Supercomputing, Rhodes, Greece, June 1999.
MESA: Reducing Cache Conflicts by Integrating Static and.. - Xiaoning Ding Dimitrios (Correct)
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T. Sherwood, B. Calder, and J. Emer. Reducing Cache Misses using Hardware and Software Page Placement. In Proc. of the 1999.
Next-Generation Memory Systems - Wang (2004) (Correct)
No context found.
T. Sherwood, B. Calder, and J. Emer. Reducing cache misses using hardware and software page placement. In Proceedings of the 1997.
Cache Optimization for Coarse Grain Task - Parallel Processing Using (Correct)
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Timothy Sherwood, Brad Calder, and Joel Ember. Reducing cache misses using hardware and software page placement. In Proc. of the International Conference of Supercomputing, June 1999.
Efficient Remapping Mechanisms for an Adaptable Memory System - Zhang (2002) (Correct)
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T. Sherwood, B. Calder, and J. Emer. Reducing cache misses using hardware and software page placement. In Proceedings of the 1999.
Compiling for Instruction Cache Performance on a.. - Kumar, Tullsen (2002) (Correct)
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T. Sherwood, B. Calder, and J. Emer. Reducing cache misses using hardware and software page placement. In ICS-99 International Conference on Suprcomputing, June 1999.
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