V. Mooney, C. Coelho, T. Sakamoto and G. De Micheli, "Synthesis From Mixed Specifications," European Design Automation Conference, pp. 114--119, September 1996. Home/Search Document Details and Download
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Java Based Modeling And Simulation Of Digital Systems On.. - Kuhn, Rosenstiel (1998) (1 citation) (Correct)
....simulation steps. Therefore, other approaches use programming languages. Olympus (Hercules) 3] and Vulcan [6] are using HardwareC. Cosyma [5] uses C. The descriptions in C are restricted to behavioral descriptions on the algorithmic level. CoWare [7] uses a combination of VHDL and C. Parnassus [4] uses C and Verilog. In Parnassus C is also used for hardware description but restricted to behavioral descriptions on the algorithmic and system level as well. Scenic [8] for example uses the object oriented language C for algorithmic descriptions. Some other approaches like [9] tend to form ....
V. J. Mooney, C. N. Coelho, T. Sakamoto, and G. DeMicheli. Synthesis From Mixed Specifications. Proceedings of the EuroDac, pp. 114-119, 1996.
Hardware/Software Co-Design of Run-Time Schedulers for.. - Mooney, III (2000) Self-citation (Mooney De micheli) (Correct)
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V. Mooney, C. Coelho, T. Sakamoto and G. De Micheli, "Synthesis From Mixed Specifications," European Design Automation Conference, pp. 114--119, September 1996.
Run-Time Scheduler Synthesis For Hardware-Software Systems.. - Mooney, De Micheli (1997) (9 citations) Self-citation (Mooney Sakamoto De micheli) (Correct)
....control synthesis for individual hardware tasks. We thus apply CFEs at a higher level of abstraction: the coordination of tasks, with a single CFE action serving as the start event for a task in hardware or software. This contrasts with earlier uses of CFEs to model systems at the operation level[10]. Using CFEs to coordinate tasks hides the coordination of lowlevel operations from the CFE model and results in greatly reduced control logic. 4.1 Task Control Flow Extraction Serra takes as input a collection of tasks described in Verilog and C. We obtain a Control Data Flow Graph for each ....
.... we obtain a CFE specification of the system which generates start events for each task (via CFE actions) 2 Serra synthesizes the control unit of the scheduler by means of tool Thalia which takes as input a CFE description and produces a logic level description in synthesizable Verilog[9, 10]. The constraints specified in the CFEs input to Thalia are translated into automata. Thus, for the control to be synthesizable, the intersection of constraints with possible state machine implementations must not be void. 5.2 Control of Software Software has a start vector and done vector which ....
V. Mooney, C. Coelho, T. Sakamoto and G. De Micheli, "Synthesis From Mixed Specifications," European Design Automation Conference, pp. 114-119, September 1996. 5
VHDL generation from SDL specifications - Daveau, Marchioro, Valderrama.. (1996) (18 citations) (Correct)
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V.J. Mooney, C.N. Coelho, T. Sakamoto and G. De Micheli, Synthesis From Mixed Specifications, Proceedings of the European Design Automation Conference with Euro-VHDL, September 1996.
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