J. Engblom, A. Ermedahl, M. Sjdin, J. Gustafsson, and H. Hansson. Towards Industry-Strength WorstCase Execution Time Analysis. Technical Report 99/02, ASTEC, 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....source code only. For example, it may not be possible to determine an upper bound on the number of iterations a loop will perform even though they are bounded, for this reason annotations are included in the code to express such bounds. For a discussion of general architecture of WCET tools see [3]. We follow the same style of annotations of the Spark Ada [1] in which annotations are introduced, mainly, for program analysis and verification. Chapman in [2] extends these annotations to perform WCET of Spark Ada. These annotations result in much tighter WCET bounds. This was achieved by ....

J. Engblom, A. Ermedahl, M. Sjodin, J. Gustafsson, and H. Hansson. Towards industry strength worst-case execution time analysis. Technical Report DoCS 109, DoCS Uppsala University, 1999.

....times of processes, as well as the communication times, to be given. In the Figure 2.1 they are depicted to the right of each node. In the case of hard real time systems this will, typically, be worst case execution times and their estimation has been extensively discussed in the literature [Eng99, Li95, Lun99, Mal97]. For many applications, actual execution times of processes are depending on the current data and or the internal state of the system. By explicitly capturing the control flow in our model, we allow for a more finetuned modeling and a tighter (less pessimistic) assignment of CHAPTER 2 14 worst ....

....our main distinction in this section will be made between non preemptive static cyclic scheduling and preemptive fixed priority scheduling. We have to mention that performance estimation and scheduling of processes typically requires, as an input, estimated execution times of single processes [Eng99, Ern97, Gon95, Hen95, Li95, Lun99, Mal97, Suz96]. Non preemptive static cyclic scheduling. Static cyclic scheduling of a set of data dependent software processes on a multiprocessor architecture has been intensively researched [Kop97a, Xu00] Several approaches are based on list scheduling heuristics using different priority criteria [Cof72, ....

J. Engblom, A. Ermedahl, M. Sjdin, J. Gustafsson, H. Hansson, "Towards Industry Strength Worst-Case Execution Time Analysis", Swedish National RealTime Conference SNART'99, 1999

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J. Engblom, A. Ermedahl, M. Sjodin, J. Gustafsson, and H. Hansson. Towards industry-strength worst case execution time analysis. Technical Report ASTEC 99/02, Advanced Software Technology Center (ASTEC), April 1999.

....and comparing the execution times. For details see [7] We do not include any cache or branch predictors in the current version of the tool, since our target system does not have a such features. The analysis method could easily be extended to include the e ects of such features as outlined in [8]. For this set of experiments, the target system was the NEC V850E [4] 32 bit embedded microcontroller. We have designed our own cycle accurate simulator for the V850E core using a generic framework, and we plan to support other architectures in the future. 7. Experiments In order to ....

J. Engblom, A. Ermedahl, M. Sjodin, J. Gustafsson, and H. Hansson. Towards industry-strength worst case execution time analysis. Technical Report ASTEC 99/02, Advanced Software Technology Center (ASTEC), April 1999.

....Examples of such effects are pipeline overlap and memory access speed. Finally, in the calculation phase the WCET estimate is calculated, given the high level and low level analysis results. For a more detailed and thorough overview of issues and work in the area of WCET analysis we refer to [15, 7]. This paper is focused on the low level estimation of WCET. Such analysis is becoming increasingly difficult due to new processor features, such as pipelines, caches, and branch prediction units. Modeling of processors timing behavior has been the way research has been approaching this ....

....certain instructions. The method provides timing information of program fragments to be combined with high level WCET analysis providing information about loop iterations and feasible paths. Hence, the method assumes a context with high level analysis and calculation methods, e.g. as proposed in [7]. The outline of the paper is as follows. In Section 2 we give an overview of our method. Section 3 describes which timing information can be derived from programs, and how this can be performed. In Section 4 we show how the method can be extended to handle pipelines and other effects related the ....

J. Engblom, A. Ermedahl, M. Sjodin, J. Gustafsson, and H. Hansson. Towards Industry Strength Worst-Case Execution Time Analysis. Technical Report 99/2, ASTEC, 1999.

....language. The method is suitable to include as a part of a general WCET tool, thus automating and simplifying the work of the real time programmer. To this end, we cooperate with IAR Systems in Uppsala, Sweden, to integrate WCET analysis in their embedded systems development environment [6]. ....

J. Engblom, A. Ermedahl, M. Sjodin, J. Gustafsson, and H. Hansson. Towards industry strength worst-case execution time analysis. Technical report, Department of Computer Systems, Uppsala University, Sweden, 1999. ASTEC Report 99/02.

....Sections 8 and 9 present conclusions and plans for future work. 2. WCET Analysis Overview and Previous Work To generate a WCET estimate, we consider a program to be processed through the phases of program flow analysis, low level analysis and calculation. For a more detailed division see [8]) The program flow analysis phase determines possible program flows, without regard to the time for each atomic unit of flow. The result of the flow analysis should provide information about which functions get called, how many times loops iterate, if there are dependencies between ....

....and comparing the execution times. For details see [7] We do not include any cache or branch predictors in the current version of the tool, since our target system does not have a such features. The analysis method could easily be extended to include the effects of such features as outlined in [8]. For this set of experiments, the target system was the NEC V850E [4] 32 bit embedded microcontroller. We have designed our own cycle accurate simulator for the V850E core using a generic framework, and we plan to support other architectures in the future. 7. Experiments In order to ....

J. Engblom, A. Ermedahl, M. Sjodin, J. Gustafsson, and H. Hansson. Towards industry-strength worst case execution time analysis. Technical Report ASTEC 99/02, Advanced Software Technology Center (ASTEC), April 1999.

....we only simulate small pieces of a program, and we do not need to modify the simulator. 3. WCET Analysis Overview The results presented in this paper should be considered in the context of our complete architecture for WCET analysis, outlined in Figure 1 (a more detailed description is given in [4]) In order to generate a WCET estimate, a program is processed through a number of modules: The compiler converts the program source code (usually C) to object code, and provides the flow analysis with access to the program code. The flow analysis determines the program flow such as loop ....

J. Engblom, A. Ermedahl, M. Sjodin, J. Gustafsson, and H. Hansson. Towards industry-strength worst case execution time analysis. Technical Report ASTEC 99/02, Advanced Software Technology Center (ASTEC), April 1999. Submitted to the Kluwer Journal of Real-Time Systems.

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J. Engblom, A. Ermedahl, M. Sjdin, J. Gustafsson, and H. Hansson. Towards Industry-Strength WorstCase Execution Time Analysis. Technical Report 99/02, ASTEC, 1999.

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