Michael S. Allen, W. Kurt Lewchuk, and John D. Coddington. A high performance bus and cache controller for powerpc multiprocessing systems. In Proceedings of the International Conference on Computer Design, pages 204--211, October 1995. Home/Search Document Not in Database Summary Related Articles |
This paper is cited in the following contexts:
Caching Coherently Work Project No. 311405-5938 - Date April From (Correct)
....suffered from bad descriptions for a while (we point out several errors and omisions in architecture textbooks and research papers at the end) We also describe a common protocol for solving that problem: the MESI protocol. The references used to compile this manuscript are [AB86, HL90, Gal91, ALC95, Ste90, CGH 92, Sta90] Typically, shared memory multiprocessor systems have a main memory that is shared by a set of processors through a bus (or for that matter a network, although we refer to it as a bus) Each processor has a private memory inserted between itself and the bus This ....
Michael S. Allen, W. Kurt Lewchuk, and John D. Coddington. A high performance bus and cache controller for powerpc multiprocessing systems. In Proceedings of the International Conference on Computer Design, pages 204--211, October 1995.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC