"Symmetry Multiprocessor Architecture Overview," Sequent Computer Systems, Inc. 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....a survey of related work from the literature. 2.1 Shared Memory Multiprocessors In this section, various shared memory multiprocessors with the different interconnection networks are surveyed. Sequent Symmetry series was one of popular shared bus multiprocessors in late 80 s to early 90 s [60]. Its largest configuration, S81, had up to thirty 80386 with the clock speed of 20MHz. In S81, all the memory and I O accesses had to go through the system bus (i.e. they were not connected to some processor(s) Therefore, this type of multiprocessor is also referred to as a symmetric ....

"Symmetry Multiprocessor Architecture Overview," Sequent Computer Systems, Inc. 1990.

....trace driven simulation. The simulator modeled a shared memory multiprocessor whose processors have multiple hardware contexts. Program traces (both data and instruction) from fourteen explicitly parallel applications were generated using the MPtrace [9] parallel tracing tool on a Sequent Symmetry [19]. Certain characteristics of the applications were extracted from the trace files and fed to the placement algorithms, which in turn produced maps associating threads with processors. Both maps and program traces were input to the simulator. The next two subsections discuss in greater detail the ....

Symmetry Technical Summary.Sequent Computer Systems.

....architecture [4] to be available soon) For comparison, we also provide performance results for a bus based symmetric shared memory multiprocessor (SSMP) the Silicon Graphics Power Challenge. The SSMP architecture is well understood and has been commercially available for a number of years [6, 7]. Although our study does not systematically use any simulation results, we will occasionally use results from the FLASHlite simulator to shed light on some observed behavior on real machines. FLASHlite simulates the FLASH machine [5] under construction at Stanford. FLASH resembles other ....

Symmetry Technical Summary. Sequent Computer Systems, Inc.

....level information in the Dynix operating system (Sequent s parallel version of the UNIX) We anticipate a core set of data collectors that will become standard, and will be provided with the IPS 2 tools. Additional collectors will be created by users for more specialized uses. The Sequent Symmetry[6] is a shared memory multi processor. Each processor has a set associative cache, and connects to main memory via the system bus. The hardware data collector ( hwEDCU ) collects metrics from special hardware monitors in the Sequent Symmetry, including utilization of the system bus, and cache miss ....

Symmetry Technical Summary, Sequent Computer Systems, Inc., 1988.

....to a user level threads library. In both types of programs, thread synchronization is performed using global barriers, and mutual exclusion is implemented with explicit lock instructions. Memory reference traces from these programs were generated from a parallel execution on a Sequent Symmetry [22] using MPtrace [8] a parallel program tracing tool. Each thread is traced separately, enabling its separate simulation in the target architecture. The trace files capture synchronization instructions, but exclude spin wait instructions, since locks may be acquired in a different order on the ....

Symmetry Technical Summary. Sequent Computer Systems, Inc.

....trace driven simulation. The simulator modeled a shared memory multiprocessor whose processors have multiple hardware contexts. Program traces (both data and instruction) from fourteen explicitly parallel applications were generated using the MPtrace [10] parallel tracing toolon a Sequent Symmetry [20]. Certain characteristics of the applications were extracted from the trace files and fed to the placement algorithms, which in turn produced maps associating threads with processors. Both maps and program traces were input to the simulator. The next two subsections discuss in greater detail the ....

Symmetry Technical Summary. Sequent Computer Systems, Inc.

....QuickThreads is designed to give modest performance. QuickThreads alone is minimalist and thus fairly fast. This section gives performance of the primitives on several platforms: an AXP [Sit93] processor, with reported timing figures estimated; one 16MHz Intel i386 processor on a Sequent Symmetry [Seq88]; a 20MHz KSR1 processor [KSR91] two SPARC based [SPA92] Suns with kernel support for register windows [Kep91] a DECstation 5000 200 using a MIPS R3000 processor [Kan87] and a VAX based [DEC81] VAXstation 3500. QuickThreads also runs on a platform using Motorola 88100 processors [Mot89] but no ....

Symmetry Technical Summary, Sequent Computer Systems, Inc., 1988.

....primitives. Details of this programming environment and examples are in the PRESTO user s manual [5] The PRESTO manual and sources can be obtained via anonymous FTP (ftp: cs.washington.edu pub presto1.0. tar.Z) The applications in this suite have been written for the Sequent Symmetry [10] and calls into the PRESTO library port to the Sequent. PRESTO s thread manipulation calls, such as thread creation, deletion, etc. are fairly standard, and are available in thread packages available on other machines. These programs are therefore easily portable to other architectures by ....

Symmetry Technical Summary. Sequent Computer Systems, Inc.

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Symmetry Technical Summary. Sequent Computer Systems, Inc. 98

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