R. Chou, K. Saluja, and V. Agrawal, Scheduling Tests for VLSI Systems Under Power Constraints, IEEE Transactions on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....proposed a test parallelization (scan chain subdivision) combining scheduling scheme to minimize test time under power limitation. However, their technique is based on a greedy algorithm which is not efficient for large SoC s with alternative test sets for each core. The readers may also refer to [3, 4, 5, 6] for other scheduling algorithms. 3. SYSTEM MODELING In this section, we describe a general SoC model, which includes not only digital cores (denoted as D cores) but analog cores (denoted as A cores) mixed signal cores (denoted as M cores) and UDLs as well (see Figure 1) Each core may have ....

R. Chou, K. Saluja, and V. Agrawal, "Scheduling tests for VLSI systems under power constraints," IEEE Trans. on VLSI Systems, vol. 5, pp. 175--185, June 1997.

.... graphcoloring) FlPo01] The graph coloring and bin packing problems cannot be approximated in bounded limits when the graph has no special structure [GaJo79] One way to simplify the test scheduling problem is to organize tests for the target modules into so called test sessions [Mur00] RaVe99] [ChSa97]. An alternative is to use a no session scheme, which allows minimizing the test time at the expense of area overhead and scheduling complexity. To reduce the scheduling time, a very fast heuristic based on the work by [FlPo01] has been used in the proposed approach (Fig. 4) The complexity of ....

....each core (from the wrapper design algorithm) and then generates in an exhaustive way all the possible hyper graphs (configurations) for the TAM. The vertices of the hyper graph correspond to the tests and are weighted by the number of connections they need on the TAM. In a similar approach in [ChSa97], the authors consider the test resources on the system and build the incompatibility graph based on them. Thus, their graph is an expression of the existing resources. In our scheme, incompatibilities, represented by the hyper edges, can be used to capture different test conflicts and ....

R. Chou, K. Saluja, V. Agrawal: "Scheduling Tests for VLSI Systems under Power Constraints", IEEE Trans. On VLSI Systems, Vol. 5, No. 2, pp. 175-185, 1997.

....computational complexity, which is an advantage since it will be used iteratively many times. Chakrabarty showed that test scheduling is equal to the open shop scheduling [4] which is known to be NP complete and the use of heuristics are therefore justified. Several heuristics have been proposed [1, 4, 7, 9, 11, 15, 23, 27]; however, they have been evaluated using rather small benchmarks. For such benchmarks, a technique based on Mixed Integer Linear Programming (MILP) can be used [7] A disadvantage is the complexity of solving the MILP model since the size of it quickly grows with the number of tests making it ....

....[12] For instance, consider a memory, which often is organized in memory banks. During normal operation, only a single bank is activated. However, during testing mode, in order to test the system in the shortest possible time it is desirable to concurrently activate as many banks as possible [9]. The use of different test resources may entail constraints on test scheduling. For instance, external testers have limitations of bandwidth due to that a scan chain operates usually at a maximum frequency of 50 MHz [13] External testers can usually only support a maximum of 8 scan chains [13] ....

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R. Chou, K. Saluja, and V. Agrawal, "Scheduling Tests for VLSI Systems Under Power Constraints," IEEE Transactions on VLSI Systems, vol. 5, no. 2, pp. 175--185, June 1997.

....resources of the ATE are properly utilized by each SOC. Methods to increase the efficiency of ATE use include test scheduling, test access mechanism (TAM) optimization, and multi site test. Test scheduling seeks to obtain an effective ordering of tests applied to the SOC to minimize testing time [2, 9]. TAM optimization is performed to improve test access to embedded cores in a modular test environment [4, 5, 7] Finally, multi site test seeks to test several copies of the SOC simultaneously on the ATE, thus reducing testing time across an entire production batch [16] While these methods ....

R. M. Chou, K. K. Saluja and V. D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Systems, vol. 5, no. 2, June 1997.

....tested prior to mounting, which is not the case for cores in core based designs. In addition, due to the design complexity, a substantial amount of test data is transported in and out of an SOC design leading to long testing times. Scheduling techniques minimizing the test time have been proposed [3,20,4,18,8,1,12,13,14]. Recently TAM scheduling, a special case of test scheduling, has gained interest [7,9] An important issue then is the wrapper used to connect the cores to the TAM [11,15,16,17] Techniques have also been proposed to reduce test power dissipation allowing testing at higher clock frequencies ....

....the tests in a system means that start time and end time are determined for all tests while satisfying all constraints minimizing the test time. Several techniques have been proposed and they can be divided into: Non partitioned testing with techniques proposed by Zorian [20] and Chou et al.[4], see Figure 1(a) Partitioned testing with run to completion with work done by Chakrabarty [3] and Muresan et al. 18] see Figure 1(b) for illustration, and . Partitioned (preemptive) testing where Iyengar and Chakrabarty [8] proposed a technique, see Figure 1(c) All approaches minimize ....

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R. Chou et al., "Scheduling Tests for VLSI Systems Under Power Constraints", IEEE Transactions on VLSI Systems, Vol. 5, No. 2, pp. 175-185,June 1997.

....and circuit type, high power dissipation during test application is due to the following: a. Systems which comprise modern memory systems and multichip modules (MCMs) employ power conscious architectural decisions where blocks are not simultaneously activated under functional operation [7]. Hence, inactive blocks do not contribute to power dissipation during the functional operation. However, when the system is in the test mode of operation, concurrent execution of tests in many blocks will result in substantially higher power dissipation when compared to functional operation. b. ....

....functional operation leading to substantially higher power dissipation. To overcome the problem of high power dissipation during test application at the system level (problem a) a powerconstrained test scheduling algorithm has been proposed for high performance memories and multichip modules [7]. The algorithm is based on a resource graph formulation for the test problem and tests are scheduled concurrently without exceeding their power ratings during test application. A new ATPG tool [21] was proposed to overcome the low correlation between consecutive test vectors during test ....

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R. Chou, K. Saluja, and V. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Transactions on VLSI, 5(2):175--184, Jun 1997.

....previous approaches for minimising power dissipation during test application in RTL data paths. To overcome the problem of high power dissipation during test application at RTL motivated by Example 2. 2, numerous power constrained test scheduling algorithms were proposed under a BIST environment [25, 41, 108, 109, 110, 132, 133, 134, 165, 167, 199]. The approach in [199] schedules the tests under power constraints by grouping and ordering based on floorplan information. A further exploration in the solution space of the scheduling problem is provided in [41] where a resource allocation graph formulation (Figure 1.8(a) from Section 1.3.2) ....

....proposed under a BIST environment [25, 41, 108, 109, 110, 132, 133, 134, 165, 167, 199] The approach in [199] schedules the tests under power constraints by grouping and ordering based on floorplan information. A further exploration in the solution space of the scheduling problem is provided in [41] where a resource allocation graph formulation (Figure 1.8(a) from Section 1.3.2) for the test scheduling problem is given and tests are scheduled concurrently without exceeding their power constraint during test application. To simplify the scheduling problem the worst case power dissipation ....

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R.M. Chou, K.K. Saluja, and V.D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2):175--184, June 1997.

....operation, special care must be taken to ensure that the power rating of the SOC is not exceeded during test application [2] A number of techniques to control power consumption in test mode have been presented in the literature. These include test scheduling algorithms under power constraints [3], low power Manuscript received April 21, 2001; revised September 13, 2001 and January 15, 2002. This work was supported in part by the National Science Foundation under Grant CCR 9875324 and in part by an equipment grant from Intel Corporation. This paper was presented in part at the Design ....

R. M. Chou, K. K. Saluja, and V. D. Agarwal, "Scheduling tests for VLSI systems under power constraints," IEEE Trans. VLSI Syst., vol. 5, pp. 175--185, June 1997.

....chains. Here, we first introduce the notion of using rectangles to model core tests, and then illustrate the flexibility in TAM design and test scheduling provided by the proposed TAM model. The use of rectangles for core test representation during test scheduling has previously been studied in [3, 5, 11]. The Design wrapper algorithm is used to obtain the different test application times for each core for varying values of TAM width. A set of rectangles for a core can now width Rectangles for Core 6 64 32 16 114317 227978 341858 (cycles) Testing time Figure 2. Example rectangles for ....

R. M. Chou, K. K. Saluja and V. D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Systems, vol. 5, no. 2, June 1997.

....TAMs, the total TAM width is explicitly partitioned among a finite number of TAMs, and each core is assigned to exactly one TAM. Such architectures are inflexible and they generally lead to inefficient usage of TAM wires [14] Several techniques for test scheduling of SOCs have been proposed [5, 7, 11, 15, 16, 18]. Methods to incorporate precedence and power constraints in a preemptive test schedule were presented in [11] These methods assume that a pre designed TAM for the SOC is provided. We address the design of an integrated framework for SOC test automation where TAM optimization and test scheduling ....

....times for each value of TAM width for a core, such that the height of the rectangle corresponds to the TAM width and the width of the rectangle represents the core test application time. The use of rectangles for core test representation during test scheduling has previously been studied in [7, 9, 10, 16]. A bin packing approach based on rectangle representation was used in [10] for test scheduling. For a given core, the testing time decreases only at Pareto optimal points when the TAM width exceeds core specific thresholds [12] Pareto optimal points are formally defined in [14] For example, ....

R.M. Chou, K.K. Saluja and V.D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Systems, vol. 5, no. 2, June 1997.

....TAMs, the total TAM width is explicitly partitioned among a finite number of TAMs, and each core is assigned to exactly one TAM. Such architectures are inflexible and they generally lead to inefficient usage of TAM wires [14] Several techniques for test scheduling of SOCs have been proposed [5, 7, 11, 15, 16, 18]. Methods to incorporate precedence and power constraints in a preemptive test schedule were presented in [11] These methods assume that a pre designed TAM for the SOC is provided. We address the design of an integrated framework for SOC test automation where TAM optimization and test scheduling ....

....times for each value of TAM width for a core, such that the height of the rectangle corresponds to the TAM width and the width of the rectangle represents the core test application time. The use of rectangles for core test representation during test scheduling has previously been studied in [7, 9, 10, 16]. A bin packing approach based on rectangle representation was used in [10] for test scheduling. For a given core, the testing time decreases only at Pareto optimal points when the TAM width exceeds core specific thresholds [12] Pareto optimal points are formally defined in [14] For example, ....

R.M. Chou, K.K. Saluja and V.D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Systems, vol. 5, no. 2, June 1997.

....SOCs use heuristics that address only certain aspects of the problem. These include selecting the best test for a core from a set of potential tests supplied by the core vendor [13] approximate vertex cover of a resource constrained test compatibility graph with a view to limit power consumption [5], and reordering of tests to detect defects earlier during manufacturing test [9] The use of test protocols [11] tree growing algorithms for power constrained scheduling [12] and integrated TAM design and test scheduling [10] are other recently Manuscript received April 11, 2001; revised ....

....scheduling as follows. Let P i denote the power dissipated when test T i alone is applied to the SOC. We define P i to be the peak power dissipated over all test patterns in T i , since this is the most realistic measure of power dissipation for the purpose of power constrained test scheduling [5]. Let overlap parameter o ij (i j) be defined as follows: o ij = 1; if tests T i and T j overlap 0; otherwise. TABLE IV POWER DISSIPATION IN TEST MODE FOR THE BIST TESTS Fig. 7. Power constrained test schedule for d5018. Let t i and t j be the start times of tests T i and T j , ....

R. M. Chou, K. K. Saluja, and V. D. Agrawal, "Scheduling tests for VLSI systems under power constraints," IEEE Trans. VLSI Syst., vol. 5, pp. 175--185, June 1997.

....of abstraction to produce further savings in power dissipation. Furthermore, new techniques for power minimization at higher levels of abstraction are required when applying BIST [7, 10] for register transfer level (RTL) data paths synthesized using high level synthesis for low power [6] In [1] a power constrained test scheduling algorithm at the system level has been presented for high performance memories and multichip modules. Despite the efficiency achieved at the system level, the algorithm cannot be applied for BIST RTL data paths due to the following two reasons. Firstly, test ....

....for BIST RTL data paths due to the following two reasons. Firstly, test scheduling for a fixed test resource allocation is solved using exact algorithms for clique identification and covering problems. Since test synthesis and test scheduling are strictly interrelated [7, 10] the formulation in [1] will lead to prohibitively large computational time hindering efficient exploration of the testable design space. Secondly, power constrained test scheduling proposed in [1] assumes fixed amount of power dissipation associated with each test. This assumption is not valid in the case of BIST RTL ....

[Article contains additional citation context not shown here]

R. Chou, K. Saluja, and V. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Transactions on VLSI, 5(2):175--184, Jun 1997.

....and circuit type, high power dissipation during test application is due to the following problems: i. Systems which comprise modern memory systems and multichip modules (MCMs) employ power conscious architectural decisions where blocks are not simultaneously activated under functional operation [6]. Hence, inactive blocks do not contribute to power dissipation during the functional operation. However, when the system is in the test mode of operation, concurrent execution of tests in many blocks will result in substantially higher power dissipation when compared to functional operation. ii. ....

....proposed solutions for solving problems (i) iii) of section 1.1. Problem (i) To overcome the problem of high power dissipation during test application at the system level , numerous power constrained test scheduling algorithms have been proposed under built in self test (BIST) environment [1, 6 11]. The approach in [1] schedules the tests under power constraints by grouping and ordering based on floorplan information. A further exploration in the solution space of the scheduling problem is provided in [6] where a resource graph formulation for the test problem is given and tests are ....

[Article contains additional citation context not shown here]

R. Chou, K. Saluja, and V. Agrawal, "Scheduling tests for VLSI systems under power constraints," IEEE Transactions on VLSI, vol. 5, pp. 175--184, Jun 1997. 28

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R. Chou, K. Saluja, and V. Agrawal, Scheduling Tests for VLSI Systems Under Power Constraints, IEEE Transactions on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.

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R. Chou, K. Saluja, and V. Agrawal, Scheduling Tests for VLSI Systems Under Power Constraints, IEEE Transactions on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.

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R. Chou, K. Saluja and and V. Agrawal, "Scheduling Tests for VLSI Systems Under Power Constraints," Trans. on VLSI, vol. 5, no. 2, pp. 175-185, June 1997.

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R. Chou, K. Saluja and and V. Agrawal, "Scheduling Tests for VLSI Systems Under Power Constraints," Trans. on VLSI, vol. 5, no. 2, pp. 175185, June 1997.

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R.M. Chou, K.K. Saluja, and V.D. Agrawal. Scheduling Tests for VLSI Systems under Power Constraints. IEEE Transactions on VLSI Systems, Vol. 5(No. 2):175--185, June 1997.

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R. M. Chou, K. K. Saluja and V. D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Systems, vol. 5, no. 2, June 1997.

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R.M. Chou, K.K. Saluja, and V.D. Agrawal, "Scheduling Tests for VLSI Systems under Power Constraints," IEEE Trans. VLSI Systems, vol. 5, no. 2, June 1997.

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R.M. Chou, K.K. Saluja and V.D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI, vol. 5, no. 2, pp. 175--184, June 1997.

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R. Chou et al., "Scheduling Tests for VLSI Systems Under Power Constraints", Transactions on VLSI Systems,Vol.5, No. 2, pp. 175-185, June 1997.

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R. Chou, K. Saluja, and V. Agrawal, "Scheduling Tests for VLSI Systems Under Power Constraints", IEEE Trans. on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.

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R. M. Chou, K. K. Saluja, and V. D. Agrawal. Scheduling Tests for VLSI Systems Under Power Constraints. IEEE Transacions on VLSI Systems, 5(2):175--185, June 1997.

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