Elbirt, A. at al.: An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. Proc. of The Third Advanced Encryption Standard Candidate Conference, NIST, Gaithersburg, MD, April 1314, (2000) 13--27  Home/Search   Document Details and Download   Summary   Related Articles   Check

....for FPGA, as proved in the next section. 7 Comparison with AES RIJNDAEL, SERPENT and MISTY1 In order to evaluate our implementation results and the hardware suitability of KHAZAD and MISTY1, we compare them with similar results obtained with the Advanced Encryption Standard RIJNDAEL and SERPENT [5]. We chose RIJNDAEL because of its status of new encryption standard and SERPENT because it seems that it was the best AES candidate regarding FPGA implementations. However, comparisons between KHAZAD and MISTY1 seem to be more relevant because they were implemented using the same methodology. In ....

....We chose RIJNDAEL because of its status of new encryption standard and SERPENT because it seems that it was the best AES candidate regarding FPGA implementations. However, comparisons between KHAZAD and MISTY1 seem to be more relevant because they were implemented using the same methodology. In [5], the Xilinx VIRTEX1000BG560 4 was selected as the target device for evaluation of AES candidates. Table 10 compare RIJNDAEL, SERPENT, MISTY1 and KHAZAD encryption circuits in terms of hardware cost, frequency and throughput. The hardware cost in LUT and registers is replaced by a number of ....

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A.J.Elbirt et Al, An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists, The Third Advanced Encryption Standard (AES3) Candidate Conference, April 13-14 2000, New York, USA.

....comparison, we report numbers based upon a circuit with 520 I O pins that uses multiple cores in parallel. Table 1. Circuit Performance Figures Transistor Gate count Cycles block Throughput Ichikawa et al. 6] 518K gates 1. 95 Gbps Weeks et al. 13] 642K transistors 606 Mbps Elbirt et al.[5] 6 300Mbps 14MHz (256 pin I O) 2.1 1.938 Gbps 32 MHz Our hardware circuit 256K gates 0.5 7.5 Gbps 32 MHz using 32 parallel cores (iterated) of 4k gates each and 252 gate levels Table 2 lists cycle counts and target architectures for various reported implementations. In our case, the ....

AJ Elbirt, W Yip, B Chetwynd and C Paar, \An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists". In Proc. Third AES Candidate Conference, April 13-14, 2000.

....is parallel processing, using either several independent execution units or pipelining. Even taking into account limitations imposed by the area of FPGA devices, pipelining was shown to permit speeding up the implementations of AES and other secret key ciphers by at least an order of magnitude [3, 9]. Taking into account the relatively smaller area required by the basic implementations of SHA 1 and SHA 512, a potential speed up is even greater in case of hash functions. Unfortunately, applying parallel processing to hash functions is limited by the fact that only input blocks belonging to ....

Elbirt, A. J., Yip, W., Chetwynd, B., Paar, C.: An FPGA implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. Proc. 3rd Advanced Encryption Standard (AES) Candidate Conference, New York, April 13-14, 2000.

....of applications. Data encryption, for example, is able to leverage both parallelism and fine grained data manipulation. An implementation of the Serpent Block Cipher in the Xilinx Virtex XCV1000 shows a throughput increase by a factor of over 18 compared to a Pentium Pro PC running at 200MHz [Elbirt00]. Additionally, a reconfigurable computing implementation of sieving for factoring large numbers (useful in breaking encoding schemes) was accelerated by a factor of 28 over a 200 MHz UltraSparc workstation [Kim00a] The Garp architecture shows a comparable speedup for DES [Hauser97] as does an ....

A. J. Elbirt, C. Paar, "An FPGA Implementation and Performance Evaluation of the Serpent Block Cipher", ACM/SIGDA International Symposium on FPGAs, pp. 33-40, 2000.

....3 7 x 5 4 modular exponential as a means of improving performance. In addition to RSA, a number of papers have been written on the subject of hardware implementation of block cipher algorithms. It appears that often these studies focus upon Field Programmable Gate Arrays (FPGA) technology[3, 7, 13]. Also, the National Security Agency has performed some excellent studies on hardware techniques for blokc cipher. Block cipher remains important as it lies in the critical path of network applications. At the same time, as the sophistication of those with malicious intent increases along with the ....

A. Elbirt, Y. Yip, B. Chetwynd, and C. Paar. An fpga implementation and performance evaluation of the aes block cipher algorithm finalists. In Proceedings of The Third Advance Encryption Standard (AES3) Candidate Conference, April 2000.

....was a good agreement among results reported by several independent groups. The above conditions were not fulfilled to the same degree by other evaluation criteria. The initial results regarding the hardware efficiency of the AES candidates were reported during the Third AES Candidate Conference [DPR00a, EYCP00, GaCh00a, IKM00, WeWa00, WBRF00a], and or submitted as official AES comments [BoCz00, Fis00, Mro00] Despite the similar approaches taken by these groups, the reported results and rankings of the AES candidates were far from uniform. Additional problem with matching and comparing the results was caused by a different terminology ....

....As shown in Table II, there is no common name for this parameter used consistently in the literature. The encryption (decryption) latency and throughput are related by: throughput = block size number of blocks processed simultaneously latency (2) 5 This paper NSA [WBRF00a, WBRF00b] WPI [EYCP00] USC [DPR00a, DPR00b] Berkeley [WeWa00] GMU [GaCh00a] Encryption (decryption) throughput Throughput Throughput Throughput Bandwidth (see equation (1) Speed, Throughput Encryption (decryption) latency Time to encrypt (decrypt) one block Latency Area Area [m 2 ] CLB ....

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A. J. Elbirt, W. Yip, B. Chetwynd, C. Paar, "An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists," Proc. 3rd Advanced Encryption Standard (AES) Candidate Conference, New York, April 13-14, 2000.

....of other secret key block ciphers. In this paper, we focus on implementing and comparing AES candidates using the reconfigurable hardware technology based on Field Programmable Gate Arrays (FPGAs) Our work supplements and extends other research efforts based on the same technology [4], 5] 6] and on the use of semi custom Application Specific Integrated Circuits (ASICs) 7] 8] 9] 2. Field Programmable Gate Arrays Field Programmable Gate Array (FPGA) is an integrated circuit that can be bought off the shelf and reconfigured by designers themselves. With each ....

....Additionally, the key scheduling unit could be easily implemented within the same device as the encryption decryption unit. In Figs. 11 and 12, we compare our results with the results of research groups from Worcester Polytechnic Institute and University of Southern California, described in [4] and [5] Both groups used identical FPGA devices, the same design tools and similar design procedure. The order of the AES algorithms in terms of the encryption and decryption throughput is identical in reports of all research groups. Serpent in architecture I8 (see Fig. 8b) and Rijndael are over ....

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A. J. Elbirt, W. Yip, B. Chetwynd, C. Paar, "An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists," in [2].

....in XCV 1000 6. This difference can be attributed to the three times smaller area requirements of DES, supporting more efficient routing, and to the more focused and careful optimizations described in [14] An architecture similar to our mixed inner and outer round pipelining was reported in [5]. The primary difference was that the number of the inner round pipeline stages k was chosen to be small, ranging from 1 to 3, leading to designs sub optimum from the point of view of both throughput and throughput to area ratio [9] Speed ups resulting from applying pipelining were from 3.4 to ....

....6. ADVANTAGES OF USING MIXED INNER AND OUTER ROUND PIPELINING FOR COMPARING PERFORMANCE OF THE AES CANDIDATES In papers presented at the Third AES Conference [13] several research groups presented their methodology for a fair comparison of the hardware performance of five AES finalists [3, 5, 8, 11, 15, 16]. For ciphers operating in the feedback cipher modes, such as CBC, CFB, OFB, a good agreement in both methodology and the results of comparison was achieved. For ciphers operating in the non feedback cipher modes, such as ECB and counter mode, methodologies used by various groups were ....

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Elbirt, A. J., Yip, W., Chetwynd, B., Paar, C. An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists, Proc. 3rd Advanced Encryption Standard (AES) Candidate Conference, New York, April 13-14, 2000.

....slice = 1 2 of a CLB) 3. NEW METHODOLOGY FOR THE DESIGN OF SECRET KEY BLOCK CIPHERS 3.1 Features of the new methodology Traditional methodology for the design of high performance implementations of secret key block ciphers is shown in Fig. 1. This methodology is discussed among the others in [4, 17]. The basic iterative architecture, shown in Fig. 1a is implemented first, and its speed and area are determined. Based on these estimations, the number of rounds, K, that can be unrolled without exceeding the available area is found. This number must be a divisor of the total number of rounds, ....

Elbirt A. J., and Paar, C. An FPGA Implementation and Performance Evaluation of the Serpent Block Cipher. Eighth ACM International Symposium on FieldProgrammable Gate Arrays, Monterey, California, February 10-11, 2000. Preprint available at http://ece.wpi.edu/Research/crypt/publications/index.html.

....Using two additional Virtex devices, and more complex architectures, the encryption throughput in excess of 3 Gbit s can be accomplished. Our 64 bit 66 MHz PCI module will support this bandwidth. 7. Related Work Several research groups developed VHDL implementations of Rijndael in Xilinx FPGAs [3, 6, 7, 12, 14], and Altera FPDs [8, 9, 10, 19] A survey and relative comparison of results from various groups is given in [13] All major results described in the aforementioned papers are based on the static timing analysis and simulation, and have not yet been confirmed experimentally. The first attempt to ....

Elbirt A. J., Yip W., Chetwynd B., Paar C.: An FPGA implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. Proc. 3rd Advanced Encryption Standard (AES) Candidate Conference, New York, April 13-14, 2000

....and the high costs and lengthy design cycles of semi or full custom integrated circuits cannot be justified. In the past, the use of programmable logic in cryptography has been limited primarily to implementations of symmetric key algorithms such as DES (e.g. 135] 105] 48] 62] and [39]) Unfortunately, asymmetric key algorithms were largely ignored as the high gate counts required for efficient implementation were not available in a single device. The latest advances in programmable logic have addressed and alleviated this constraint by delivering devices with usable gate ....

A.J. Elbirt, W. Yip, B. Chetwynd, and C. Paar, "An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists," Third Advanced Encryption Standard (AES) Conference, 2000.

....The XOR, mod 2 32 add and subtract, and fixed shift operations are fast and use few hardware resources. The GF(2 8 ) multiplications used by the finalists are also efficient. The most costly operation in terms of both area and time is mod 2 32 multiplication. 3.5.3.2 A Case Study In Ref. [30], all finalists except MARS were implemented using FPGAs. However, only the encryption function was implemented. It was assumed that subkeys were generated externally, loaded from the external key bus, and stored in internal registers before encryption began. 3 VHDL stands for VHSIC Hardware ....

....(FPGA Express by Synopsis, Inc. and Synplify by Synplicity, Inc. were set to optimize the implementation for speed. For internally pipelined architectures, a 40 MHz timing constraint was used. Note: The terms basic architecture, external pipelining and internal pipelining are referred to in Ref. [30] as iterative looping, partial pipelining and sub pipelining, respectively. 3.5.3.2.1 Notes on the Four Finalists Implemented RC6: Although RC6 can use a mod 2 32 multiplier, a simpler structure called an array squarer was all that was needed. The array squarer reduced the logic required for ....

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A. Elbirt, et al., An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists, in The Third AES Candidate Conference, printed by the National Institute of Standards and Technology, Gaithersburg, MD, April 13-14, 2000, pp. 13-27.

....[1] to form the cryptographic library. We have chosen these algorithms because of the projected key role of AES in protecting electronic data flow. Each algorithm was implemented using the Virtex FPGA series devices [17] For each implementation, we provide precise time performance results. In [6] and [15] only the cryptographic cores of three final candidate algorithms (Serpent, RC6, Twofish) were implemented. However, in both papers [6, 15] no results were provided regarding the key setup of the algorithms. In our implementations, besides throughput results, we provide key setup ....

....flow. Each algorithm was implemented using the Virtex FPGA series devices [17] For each implementation, we provide precise time performance results. In [6] and [15] only the cryptographic cores of three final candidate algorithms (Serpent, RC6, Twofish) were implemented. However, in both papers [6, 15], no results were provided regarding the key setup of the algorithms. In our implementations, besides throughput results, we provide key setup latency results. The latency metric is the key measure for IPSec where a small amount of data is processed per key and key context switching occurs ....

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A. J. Elbirt, C. Paar, "An FPGA Implementation and Performance Evaluation of the Serpent Block Cipher", Eighth ACM International Symposium on Field-Programmable Gate Arrays, February 2000.

....the inherent parallelism of the cryptographic core (at the round level) to optimize performance. Moreover, we have exploited the low level hardware features of FPGAs to enhance the performance of individual required operations. Our throughput results are compared with the FPGA based results in [9, 11]. In [9, 11] only the cryptographic core of each algorithm was implemented using FPGAs and, thus, no key setup latency results were provided. As a result, only throughput comparisons are made with the FPGA based results in [9, 11] Moreover, our time performance results are compared with the best ....

....parallelism of the cryptographic core (at the round level) to optimize performance. Moreover, we have exploited the low level hardware features of FPGAs to enhance the performance of individual required operations. Our throughput results are compared with the FPGA based results in [9, 11] In [9, 11], only the cryptographic core of each algorithm was implemented using FPGAs and, thus, no key setup latency results were provided. As a result, only throughput comparisons are made with the FPGA based results in [9, 11] Moreover, our time performance results are compared with the best ....

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A. J. Elbirt, W. Yip, B. Chetwynd, and C. Paar, \An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists", Third AES Candidate Conference, April 2000.

....using the CryptoBooster architecture achieved theoretical of 200 Mbps for single round implementations and 1. 5 Gbps for implementations that are both fully un rolled and pipelined [104] Multiple FPGA implementation studies have been presented for the AES candidate algo rithm finalists [38, 39, 49, 50, 57, 141, 145], the results of which are found in Table 2.2. Note that [50] is a subset of the study performed in [49] and that no throughput results are presented in [145] The studies performed in [49, 50, 57] used a Xilinx Virtex XCV1000 4 as the target FPGA. The study performed in [38, 39] used the Xilinx ....

....implementations and 1.5 Gbps for implementations that are both fully un rolled and pipelined [104] Multiple FPGA implementation studies have been presented for the AES candidate algo rithm finalists [38, 39, 49, 50, 57, 141, 145] the results of which are found in Table 2.2. Note that [50] is a subset of the study performed in [49] and that no throughput results are presented in [145] The studies performed in [49, 50, 57] used a Xilinx Virtex XCV1000 4 as the target FPGA. The study performed in [38, 39] used the Xilinx Virtex family of FPGAs but did not specify which FPGA was used ....

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A. Elbirt, W. Yip, B. Chetwynd, and C. Paar. An FPGA Implementation and Per- formance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. In The Third Advanced Encryption Standard Candidate Conference, pages 13-27, New York, New York, USA, April 13-14 2000. National Institute of Standards and Technology.

....achieved throughputs of 11.03 Mbps using a Xilinx Virtex XCV1000 4 [47] and 13 Mbps using a Xilinx XC4020XV 9 [117] An RC6 implementation achieved a throughput of 37 Mbps using a Xilinx XC4020XV 9 [117] A Serpent implementation using a Xilinx Virtex XCV1000 4 achieved a throughput of 4. 86 Gbps [48]. When targeted to a Xilinx Virtex E XCV400E 8, a Serpent implementa tion achieved a throughput of 17.55 Gbps through the use of the Xilinx run time reconfigu ration software application JBits TM which allowed for real time key specific compilation of the bit stream used to program the FPGA ....

.... Xilinx run time reconfigu ration software application JBits TM which allowed for real time key specific compilation of the bit stream used to program the FPGA [112] This run time reconfiguration resulted in a smaller and faster design (which operated at 137.15 MHz) as compared to the design in [48] (which operated at 37.97 MHz) When implemented using an FPGA from the Altera Flex 10KA family, the Serpent algorithm achieved a maximum throughput of 301 Mbps [108] However, it is important to note that the implementation in [108] implements eight of the Serpent algorithm s thirty two rounds ....

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A. Elbirt and C. Paar. An FPGA Implementation and Performance Evaluation of the Serpent Block Cipher. In FPGA '00 - ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 33-40, Monterey, CA, USA, February 2000. ACM.

....algorithm finalists FPGA implementation studies best performance results FPGA implementations of individual candidate algorithms (both finalists and non finalists) have also been performed. Implementations of CAST 256 achieved throughputs of 11.03 Mbps using a Xilinx Virtex XCV1000 4 [47] and 13 Mbps using a Xilinx XC4020XV 9 [117] An RC6 implementation achieved a throughput of 37 Mbps using a Xilinx XC4020XV 9 [117] A Serpent implementation using a Xilinx Virtex XCV1000 4 achieved a throughput of 4.86 Gbps [48] When targeted to a Xilinx Virtex E XCV400E 8, a Serpent ....

....is then synthesized and optimized into a gate level netlist which is then placed and routed, resulting ultimately in a bitstream used to program the function units and the interconnect matrix of the FPGA. Multiple FPGA based implementations of block ciphers have appeared throughout the literature [38, 47, 48, 49, 50, 54, 57, 78, 79, 80, 99, 104, 111, 112, 113, 117, 140, 145]. FPGAs can provide algorithm agility due to their ability to be reprogrammed as needed. Typically, FPGA implementations do not provide as high a throughput as compared to ASIC implementations and tend to be expensive for high volume applications. ASICs are custom devices designed for a specific ....

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A. Elbirt. An FPGA Implementation and Performance Evaluation of the CAST-256 Block Cipher. Technical Report, Cryptography and Information Security Group, ECE Department, Worcester Polytechnic Institute, Worcester, Massachusetts, USA, May 1999.

....the 528 Mbit s throughput was achieved in a fully pipelined architecture, the implementation required four Xilinx XC4000 FPGAs. Some FPGA implementation throughputs for the AES candidates have been shown to be far slower than their software counterparts. Hardware throughputs of about 12 Mbit s [12] [13] have been achieved for CAST 256. However, software implementations have resulted in throughputs of 37.8 Mbit s for CAST 256 on a 200 MHz PentiumPro PC [5] a factor of three faster than FPGA implementations. When scaled to a more current 600 MHz PentiumPro PC, it is expected that the same ....

....for a regular layout of design elements as well as to minimize the routing required between configurable units. Finally, it is critical that fast carry chaining be provided between the FPGA s configurable units to maximize the performance of AES finalists that utilize arithmetic operations [13] [12]. In addition to architectural requirements, scalability and cost must be considered. We believe that the chosen FPGA should be the best chip available, capable of providing the largest amount of hardware resources as well as being highly flexible so as to yield optimal performance. ....

A. Elbirt, "An FPGA Implementation and Performance Evaluation of the CAST-256 Block Cipher," Technical Report, Cryptography and Information Security Group, Electrical and Computer Engineering Department, Worcester Polytechnic Institute, Worcester, MA, May 1999.

....FPGA implementations by an even larger factor. While an FPGA implementation of RC6 has been shown to operate at data rates of 37.8 Mbit s [15] our findings indicate that considerably higher data rates are achievable. Additional FPGA implementation studies of the AES finalists may be found in [16] [17] [18] 19] When examining the AES finalists, it is important to note that they do not necessarily exhibit similar behavior to DES when comparing hardware and software implementations. One reason for this is that the AES finalists have been designed with e#cient software implementations in mind. ....

A. Elbirt, W. Yip, B. Chetwynd, and C. Paar, "An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists," in The Third Advanced Encryption Standard Candidate Conference, (New York, New York, USA), pp. 13--27, National Institute of Standards and Technology, April 13--14 2000.

....the 528 Mbit s throughput was achieved in a fully pipelined architecture, the implementation required four Xilinx XC4000 FPGAs. Some FPGA implementation throughputs for the AES candidates have been shown to be far slower than their software counterparts. Hardware throughputs of about 12 Mbit s [14] [15] have been achieved for CAST 256. However, software implementations have resulted in throughputs of 37.8 Mbit s for CAST 256 on a 200 MHz PentiumPro PC [6] a factor of three faster than FPGA implementations. When scaled to a more current 600 MHz PentiumPro PC, it is expected that the same ....

....for a regular layout of design elements as well as to minimize the routing required between configurable units. Finally, it is critical that fast carry chaining be provided between the FPGA s configurable units to maximize the performance of AES finalists that utilize arithmetic operations [15] [14], a feature commonly available in commercial FPGAs at no additional cost. In addition to architectural requirements, scalability and cost must also be considered. We believe that the chosen FPGA should be the most high end chip available, capable of providing the largest amount of hardware ....

A. Elbirt, "An FPGA Implementation and Performance Evaluation of the CAST-256 Block Cipher," Technical Report, Cryptography and Information Security Group, ECE Department, Worcester Polytechnic Institute, Worcester, Massachusetts, USA, May 1999.

....the 528 Mbit s throughput was achieved in a fully pipelined architecture, the implementation required four Xilinx XC4000 FPGAs. Some FPGA implementation throughputs for the AES candidates have been shown to be far slower than their software counterparts. Hardware throughputs of about 12 Mbit s [12] [13] have been achieved for CAST 256. However, software implementations have resulted in throughputs of 37.8 Mbit s for CAST 256 on a 200 MHz PentiumPro PC [5] a factor of three faster than FPGA implementations. When scaled to a more current 600 MHz PentiumPro PC, it is expected that the same ....

....for a regular layout of design elements as well as to minimize the routing required between configurable units. Finally, it is critical that fast carry chaining be provided between the FPGA s configurable units to maximize the performance of AES finalists that utilize arithmetic operations [13] [12]. In addition to architectural requirements, scalability and cost must be considered. We believe that the chosen FPGA should be the best chip available, capable of providing the largest amount of hardware resources as well as being highly flexible so as to yield optimal performance. ....

A. Elbirt, "An FPGA Implementation and Performance Evaluation of the CAST-256 Block Cipher," Technical Report, Cryptography and Information Security Group, Electrical and Computer Engineering Department, Worcester Polytechnic Institute, Worcester, MA, May 1999.

....of IDEA are able to achieve higher clock frequencies and therefore higher throughputs as there is less routing congestion. Some FPGA implementation throughputs for the AES candidates have been shown to be far slower than their software counterparts. Hardware throughputs of about 12 Mbit s [14] [13] have been achieved for CAST 256. However, software implementations have resulted in throughputs of 37.8 Mbit s for CAST 256 on a 200 MHz PentiumPro PC [6] a factor of three faster on average than FPGA implementations. These results were an important indication for us to investigate other ....

....minimize the routing required between configurable units. Finally, note that the Serpent algorithm employs no arithmetic operations in any part of the cipher. This feature minimizes the need for fast carry chaining that is needed to maximize the performance of other AES candidate algorithms [13] [14]. Based on the aforementioned considerations, the Xilinx Virtex XCV1000BG560 4 FPGA was chosen as the target device. The XCV1000 has 128K bits of embedded RAM divided among thirty two RAM blocks that are separate from the main body of the FPGA. The 560 pin ball grid array package provides 512 ....

A. Elbirt, "An FPGA Implementation and Performance Evaluation of the CAST-256 Block Cipher," Technical Report, Cryptography and Information Security Group, Electrical and Computer Engineering Department, Worcester Polytechnic Institute, Worcester, MA, May 1999.

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Elbirt, A. at al.: An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. Proc. of The Third Advanced Encryption Standard Candidate Conference, NIST, Gaithersburg, MD, April 1314, (2000) 13--27

No context found.

A. Elbirt, W. Yip, B. Chetwynd, and C. Paar. An fpga implementation and performance evaluation of the aes block cipher candidate algorithm finalists. In The Third Advanced Encryption Standard (AES3) Candidate Conference, Apr. 2000.

No context found.

A.J. Elbirt and C. Paar, "An FPGA Implementation and Performance Evaluation of the Serpent Block Cipher," Eighth ACM International Symposium on FieldProgrammable Gate Arrays, Monterey, California, February 10-11, 2000. Preprint available at http://ece.wpi.edu/Research/crypt/publications/index.html.

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A. Elbirt, W. Yip, B. Chetwynd, and C. Paar. An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm #nalists. Proceedings of 3rd AES conference, New York, pages 13-27, April 2000.

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