M. J. Wirthlin and B. L. Hutchings, "Improving functional density through run-time constant propagation," in Proc. 5th Int. Symp. FPGAs, 1997, pp. 86--92.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....architectures which are utilized for speeding up specific applications are replacing some ASICs. Some applications also exploit optimization based on a specific input instance of the computation. ffl Algorithmic Synthesis [52] 53] 54] 55] 56] 57] 58] 59] 60] 61] 62] 63] [64]: Dynamically reconfigurable architectures give rise to new classes of problems in mapping computations onto the architectures. New algorithmic techniques are needed to schedule the computations. Existing algorithmic mapping techniques focus primarily on loops in general purpose programs. Loop ....

M. J. Wirthlin and B. L. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation," in ACM International Symposium on Field Programmable Gate Arrays, February 1997, pp. 86--92.

....models of the configuration controller for a particular dynamic design are produced for simulation and hardware synthesis. 1 Introduction Proponents of dynamically reconfigurable logic (DRL) cite increased circuit speeds and reduced hardware requirements as two major benefits of the technique [1]. These benefits are extremely susceptible to the overheads associated with the control unit used to manage the reconfigurable aspects of the design. Some increase in physical resource requirements and decrease in system execution speed are inevitable, but the extent of these overheads depends on ....

M. J. Wirthlin and B. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation", In ACM/SIGDA International Symposium on FPGAs, pp. 86-92. 1997

....XC6216 FPGA and is the target for the dynamically reconfigurable application. The application implements a pattern matching algorithm, which requires intratask reconfiguration. The algorithm is based on a concept known as data folding [6] or more recently known as run time constant propagation [7]. The principle of data folding is quite simple: fixed coefficient implementations of circuits such as pattern matchers or multiplication units execute more quickly, in a smaller area, than the equivalent variable coefficient implementations. Data folding exploits this speed and area advantage of ....

M. J. Wirthlin and B. Hutchings, Improving Functional Density Through Run-Time Constant Propagation, In 1997.

....this paper in reference to compilation optimizations for general reconfigurable systems. Run time partial evaluation allows for the further exploitation of constants because the configurations can be modified based not only on completely static values, but also those that change slowly over time [Burns97, Luk97a, Payne97, Wirthlin97, Chu98, McKay99]. This gives reconfigurable circuits the potential to achieve an even higher performance than an ASIC, which must retain generality in these situations. The circuit in the reconfigurable system can be customized to the application at a given time, rather than to the application as a category. For ....

M. J. Wirthlin, B. L. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation", ACM/SIGDA International Symposium on FPGAs, pp. 86-92, 1997.

....that may not have been able to fit completely onto the fabric can be partitioned and executed on this virtual hardware. This potentially allows a larger percentage of a program to be accelerated in hardware than could be accelerated without RTR, increasing the benefits of runtime reconfiguration [Wirthlin97]. However, the cost of reconfiguration can be quite high. In some situations, configuration overhead can comprise over 98.5 of execution time [Smith99] This amount of overhead has the potential to eclipse the benefits gained through use of the reconfigurable hardware in RTR applications. ....

M. J. Wirthlin, "Improving Functional Density Through Run-Time Circuit Reconfiguration", PhD Thesis, Electrical and Computer Engineering Department, Brigham Young University, 1997.

....faster than programming the complete device and reconfiguration time is the order of 1 micro second. This partial reconfiguration can be done without functional interruption of the remaining parts of the device. These features of the CLAy devices have been exploited in designing novel applications [80]. 24 2.2.4 Xilinx Virtex Virtex is one of the latest in a series of high performanceFPGAs from Xilinx [83] It has different versions which have capacities ranging from 50 thousand to 1 million system gates. Virtex architecture comprises of an array of Configurable Logic Blocks (CLBs) encircled ....

....# Applications [3, 23, 29, 60, 63, 69, 85] Specialized configurable architectures which are utilized for speeding up specific applications are replacing some ASICs. 59 Some applications also exploit optimization based on a specific input instance of the computation. # Algorithmic Synthesis [5, 11, 15, 19, 21, 22, 28, 44, 45, 50, 53, 59, 62, 71, 76, 78, 80]: Dynamically reconfigurable architectures give rise to new classes of problems in mapping computationsonto the architectures. New algorithmic techniques are needed to schedule the computations. Existing algorithmic mapping techniques focus primarily on loops in general purpose programs. Loop ....

M. J. Wirthlin and B. L. Hutchings. Improving Functional Density Through RunTime Constant Propagation. In ACM International Symposium on Field Programmable Gate Arrays, pages 86--92, February 1997.

....on FPGAs. Other examples of constant propagation include the modification of ATM switch schedulers to account for virtual circuit priority [15] and DES hardware customized to specific encryption keys [16] Hutchings has advanced constant propagation further, through localized circuit replacement [17]. His group has invested some effort in the Sandia ATR problem [18] They were able to design customized pixel circuits image correlation which were approximately 30 smaller than a corresponding circuit that could be programmed to handle either case. By using the ability to partially reconfigure ....

M. J. Wirthlin and B. L. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation," Proc. of Field Programmable Gate Arrays, Monterey, CA, 1997.

....Circuit Specialization Constant propagation has long been used in software and hardware compilers to optimize programs or circuit designs. The advent of recon gurable hardware has opened the opportunity to propagate values which are not constant, thereby reducing a design s delay and area [32]. Whenever a value changes, the circuit is recon gured. Rather than changing the input of exible operators, a design which exploits run time recon guration (RTR) uses smaller operators obtained by constant propagation. Hence more of a program s operators can be implemented on a given hardware ....

M. J. Wirthlin and B. L. Hutchings, \Improving functional density through run-time constant propagation," in ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Feb. 1997, ACM Press.

....ffl Applications [2, 19, 23, 49, 51, 54, 66] Specialized configurable architectures which are utilized for speeding up specific applications are replacing some ASICs. Some applications also exploit optimization based on a specific input instance of the computation. ffl Algorithmic Synthesis [3, 9, 12, 17, 18, 22, 38, 41, 48, 50, 57, 61, 62]: Dynamically reconfigurable architectures give rise to new classes of problems in mapping computations onto the architectures. New algorithmic techniques are needed to schedule the computations. Existing algorithmic mapping techniques focus primarily on loops in general purpose programs. Loop ....

M. J. Wirthlin and B. L. Hutchings. Improving Functional Density Through Run-Time Constant Propagation. In ACM International Symposium on Field Programmable Gate Arrays, pages 86--92, February 1997.

....this paper in reference to compilation optimizations for general reconfigurable systems. Run time partial evaluation allows for the further exploitation of constants because the configurations can be modified based not only on completely static values, but also those that change slowly over time [Burns97, Luk97a, Payne97, Wirthlin97, Chu98, McKay99]. This gives reconfigurable circuits the potential to achieve an even higher performance than an ASIC, which must retain generality in these situations. The circuit in the reconfigurable system can be customized to the application at a given time, rather than to the application as a category. For ....

M. J. Wirthlin, B. L. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation", ACM/SIGDA International Symposium on FPGAs, pp. 86-92, 1997.

....Circuit Specialization Constant propagation has long been used in software and hardware compilers to optimize programs or circuit designs. The advent of recon gurable hardware has opened the opportunity to propagate values which are not constant, thereby reducing a design s delay and area [12]. Whenever a value changes, the circuit is recon gured. Rather than changing the input of exible operators, a design which exploits run time recon guration (RTR) uses smaller operators obtained by constant propagation. Hence more of a program s operators can be implemented on a given hardware ....

M.J. Wirthlin and B.L. Hutchings. Improving functional density through run-time constant propagation. In Proc. FPGA'97. ACM Press, February 1997.

....bases. An important criterion in context of reconfigurability is the functional density FD, which expresses the efficiency of the system in terms of both area and time and is defined as the number of operations n executed within the time slice Tn on a unit of silicon of size A: FD = n ATn [7]. An additional metric for the efficiency is the performance cost ratio. The following example illustrates the relevancy of the efficiency oriented performance evaluation (for a detailed description of the experiment discussed below see [8] A benchmark set consisting of three digital signal ....

Wirthlin, M.J.: Improving Functional Density Through Run-Time Circuit Reconfiguration, Ph.D. thesis, Brigham Young University (1997)

.... Algorithm level configuration Agile crypto[22] Environment dependent radar[13] ffl Algorithm Parameters configuration Motion estimation[11] Modem equalizer parameters [26] ffl Architectural level configuration DISC[15] ffl Hard wiring Automatic Target Recognition[12] Hard wired filters [19], Hard wired crypto keys[21] In the following section, several different types of configuration methods are explained briefly and matched to the list above. ffl Full Configuration The first and most typical configuration method for FPGAs is full configuration. The entire FPGA should be ....

....most fundamental of DSP algorithms. Digital filters can be implemented in many ways. Programmable DSPs lie at one end of the spectrum and dedicated ASICs the other end. FPGAs can also efficiently implement digital filters and several recent efforts have explored reconfigurable implementations [9] [19]. A key idea in reconfigurable filters is the distinction between the configuration of the filter coefficients (which has no regularity) versus the configuration of the filter length and word lengths for both data and coefficients (usually results in regular interconnections) This idea also ....

[Article contains additional citation context not shown here]

M.J. Wirthlin and B.L. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation ", FPGA`97, 1997.

....by Application Context Specific Module. An example of such system functionality extension would be partial evaluation, as discussed in section 2.2. An alternative and simpler example is a Specialisation Module effecting constant propagation a standard optimisation performed at compile time [13]. Known inputs are fed through the circuit and logic optimisation is performed e.g. an AND gate with one high input can be replaced by a wire driven by the second input. Although this not core system functionality, it may be profitable, in some application contexts, to perform this kind of ....

Michael J. Wirthlin, Brad L. Hutchings. Improving functional density through run-time constant propagation. To be published in FPGA'97.

....faster than programming the complete device and reconfiguration time is the order of 1 micro second. This partial reconfiguration can be done without functional interruption of the remaining parts of the device. These features of the CLAy devices have been exploited in designing novel applications [35]. 5 Conclusion Configurable computing holds lot of promise for the future. To realize this potential we need a variety of system architectures, algorithmic techniques and software tools. We have discussed the abstract models of reconfigurable architectures and algorithms using these models. The ....

M. J. Wirthlin and B. L. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation", ACM International Symposium on Field Programmable Gate Arrays, pp. 86-92, February 1997.

.... to date, FPGAs have been found to be reasonable alternatives to custom hardware (ASICs) or software implementations of applications they provide speed ups over software through hardware specialization while still providing the flexibility to adapt the hardware to changing application needs [12]. A large fraction of the solutions reported in the research community have focused on smaller computational problems problems for which one or a handful of general purpose processors (GPPs) or digital signal processors (DSPs) could be used to compute the results in a reasonable amount of ....

WIRTHLIN, M. J., AND HUTCHINGS, B. L. Improving functional density through run-time constant propagation. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays (Monterey, CA, Feb. 1997), pp. 86-- 92.

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M. J. Wirthlin and B. L. Hutchings, "Improving functional density through runtime constant propagation", in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, Feb. 1997, pp. 86--92. 229

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M. J. Wirthlin and B. L. Hutchings. Improving functional density through run-time constant propagation. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 86--92, Monterey, CA, Feb. 1997.

.... used to describe and execute several real applications, such as the shapesum and correlation functions of the Chunky SLD Automatic Target Recognition (ATR) problem [8] These applications have been implemented on the Xilinx 6200 using partial reconfiguration, as well as on other platforms [10]. For this initial feasibility study, the original circuits are being used as they were originally implemented via schematic capture and manual placement. The main difference is that the entire circuit is now described in JHDL. This description provides a comprehensive simulation model of the ATR ....

....is that the entire circuit is now described in JHDL. This description provides a comprehensive simulation model of the ATR application. This is itself noteworthy as the ATR application consists of several partial configurations that are loaded into FPGA devices as new images are correlated [10]. In addition, this same JHDL description is used to directly control the VCC Hotworks CCM, replacing the original Tcl Tk program that was previously used for controlling the CCM. Because netlisting capability is not yet present in JHDL, the correspondence between JHDL circuit object and ....

M. J. Wirthlin and B. L. Hutchings. Improving functional density through run-time constant propagation. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 86--92, Monterey, CA, February 1997.

....matching computation, run time reconfiguration can be used to preserve the special purpose nature of the constantpropagated circuit described in Appendix A. This section will discuss and analyze the use of run time reconfiguration within the bit serial, template matching circuit introduced in [96] and described in Appendix A. 5.3.1 System Architecture The automatic target recognition system of the Sandia National Laboratories involves three computationally intensive stages: focus of attention, second level detection, and final identification [95] The template matching system described ....

....recognition system (ATR) 95] The parallelism, fine granularity, and regularity of this operation make it an ideal candidate for CCM architectures. Several systems demonstrate the advantages of using CCM technology for this application by exploiting unique and innovative implementation techniques [80, 95, 113, 96]. This section will describe the implementation details of a bit serial approach to this algorithm that exploits the benefits of constant propagation [96] The template matching circuit described in this section is based on the computation of the cross correlation between an image, f , and a ....

[Article contains additional citation context not shown here]

M. J. Wirthlin and B. L. Hutchings. Improving functional density through run-time constant propagation. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 86--92, Monterey, CA, February 1997.

No context found.

M. J. Wirthlin and B. L. Hutchings, "Improving functional density through run-time constant propagation," in Proc. 5th Int. Symp. FPGAs, 1997, pp. 86--92.

No context found.

M. J. Wirthlin, "Improving functional density through Run-time Circuit Reconfiguration", PhD Thesis, Electrical and Computer Engineering Dept, Brigham Young Univesity, 1997.

No context found.

Michael J. Wirthlin, Improving Functional Density Through Run-Time Circuit Reconfiguration, Ph.D. thesis, 1997.

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Michael J. Wirthlin and Brad L. Hutchings. Improving Functional Density Through Run-Time Constant Propagation. FPGA'97. 1997.

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