N. T. Jarwala and D. K. Pradhan, "TRAM: A design methodology for high-performance, easily testable, multimegabit RAM's," IEEE Trans. Comput., vol. 37, pp. 1235--1250, Oct. 1988. Home/Search Document Not in Database Summary Related Articles Check |
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Algorithms and Architectures for use with Nanoelectronic.. - Forshaw (1999) (Correct)
....does not consider these two options further. 2.1.2. Clock distribution As device speeds increase, clock frequency limitations will have increasingly severe effects on what architectures are feasible with conventional digital logic, and hence on algorithm performance. It is wellknown (e.g. 46] [80], SIA 1994 Road Map) that reductions in wire cross sections will make it impractical to propagate clocked digital signals over long distances. Even if clock or data signals were propagated at the velocity of light, it would only be possible, from a single source, to provide synchronous signals ....
....obtained a crude estimate of the minimum possible delay for the adder, we now consider the delays involved in accessing the cache memory. This is a complicated subject, and so for the present we base the following illustrative calculation on the classic four quadrant memory structure (e.g. 47] [80], 86] We assume that the memory consists of a square array of L word 1 2 by L word 1 2 units, with each unit being a four quadrant memory containing N word bits of storage. The time to retrieve one bit of data from one of these units will be the sum of the times for address line decode, ....
N.T. Jarwala & D.K. Pradhan, "TRAM: a design methodology for high-performance, easily testable, multibit RAMs", IEEE Trans. Comput. 37, 1235-1250, 1988
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED.. - Ram Design With Self-citation (Pradhan) (Correct)
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N. T. Jarwala and D. K. Pradhan, "TRAM: A design methodology for high-performance, easily testable, multimegabit RAM's," IEEE Trans. Comput., vol. 37, pp. 1235--1250, Oct. 1988.
LPRAM: A Novel Low Power RAM Design with Testability - Bhattacharjee, Pradhan Self-citation (Pradhan) (Correct)
No context found.
Najmi T. Jarwala, D. K. Pradhan: "TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's", IEEE Transactions on Computers, vol. 37, no. 10, pp. 1235-1250, October 1988.
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