Heath J.R., P.J. Kuekes, G.S. Snider, and R.S. Williams. 1999. A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology. Science 280:1716-1721.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....scales with defect rate and fabric size. We present the theory underlying our method, and candidate circuit implementations for carrying out the tests. 2 Related Work Similar defect tolerance issues have been dealt with in custom computing systems (e.g. 1, 2, 3] The Teramac custom computer ([4, 1]) is the most notable example: upto 75 of the FPGAs used in the Teramac were defective. Assembly was followed by a testing phase where the defects in the FPGAs were identified and mapped. Compilers for generating FPGA configurations used this defect map to avoid the defects. Our proposed testing ....

J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology," Science, vol. 280, pp. 1716--1721, June 12 1998.

.... than in the absence of failures, since a fraction of the layers has to be devoted to correction [7] 8] Current fault tolerant techniques are basically built on redundancy technologies: tuple modular redundancy (NMR) 1] e.g. triple modular redundancy or TMR [9] reconfiguration [10], 11] A reconfigurable architecture is a computer architecture which can be configured or programmed after fabrication to implement desired computations. Faulty components are detected during testing and excluded during reconfiguration. Reconfigurable computers have been successfully ....

J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A defect -tolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, pp. 1716--1721, 1998.

....patterns of nanometer scale Au clusters. Neighboring clusters are electronically coupled and all clusters are also coupled to the underlying semiconductor substrate. Coupling is achieved through molecules that can be doped or programmed to conduct fifty times more than non doped molecules. In [3] [6] self assembled crossbar like systems are described. They consist of intersecting nanowires that contain programmable switches at each node. The switches are either electrostatic or molecular in nature they are created by simply running a wire perpendicular to another wire and possibly ....

....vertical lines of different height, whereas the connections in the second layer are all parallel stair like patterns. In both cases, the connectivity patterns require minimal programmability of individual molecules, and would also be easy to implement in the crossbar structures described in [3] [6] Heuristics can be used to generate feasible allocations of grid nodes and paths to neurons and weights. In the worst case, they mn in time proportional to the cubic power of the number of neurons. The choice of heuristic depends on specifics of the molecular grids and switches. In ....

Heath, J., Kuekes, P., Snider, G., Williams, R.S., A DefectTolerant Computer Architecture: Opportunities for Nanotechnology, Science, vol. 280, p. 1716 (1998).

....make systems based on nanometer scale devices reliable, therefore, faulttolerant architectures will be necessary. Current fault tolerant techniques are basically built on redundancy technologies: R fold Modular Redundancy (RMR) 1] e.g. Triple Modular Redundancy or TMR [2] Recon#guration [3] [4] With RMR the effect of modest transient errors are effectively eliminated, however some critical components (e.g. the Majority Voting logic in TMR) have to be highly reliable. Recon#gurable computers have been successfully implemented in protecting against permanent errors, which are mainly ....

J. R. Heath, P. J. Kuekes, G. S. Snider and R. S. Williams, A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology, Science 280, 1716-1721 (1998).

....2One compelling demonstration of this approach is the Hewlett Packard Laboratories Teramac, a mas sively parallel computer constructed fi om defective chips, which can reconfigure itself and its communication paths to avoid the broken parts and compensate for irregular interconnections. [7] Although Teramac is built fi om conventional chips, Teramac s disigners view it as a prototype architecture for designing nanoscale computers that would be assembled by chemical processes, where a significant fraction of the parts might be defective. In addition to new programming methodologies, ....

James R. Heath, Philip J. Keukes, Gregory S. Snider, R. Stanley Williams, "A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology," Science, 280 (5370): 1716.

....since we expect that every chip will have a significant number of defects. Instead, we will have to devise a way to use defective chips. A natural solution is suggested by looking at reconfigurable fabrics, i.e. Field programmable gate arrays (FPGAs) and the work on the Teramac custom computer [4, 5]. An FPGA is an interconnected set of programmable logic elements. Both the interconnect and logic elements may be programmed, or configured, to implement any circuit. The Teramac is essentially a very large FPGA with a very rich interconnect that works in spite of the fact that 75 of the chips ....

....just for memories but for logic too, where simple row replacement will not work since logic is less regular. Problems similar to this have been addressed in the domain of custom computing systems. For example, the Piperench reconfigurable processor [6] and more notably the Teramac custom computer [4, 5] had a notion of testing, defectmapping and defect avoidance built into them. Upto 75 of the FPGAs used in the Teramac were defective; assembly was followed by a testing phase where the defects in the FPGAs were identified and mapped. Compilers for generating FPGA configurations then use this ....

J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology," Science, vol. 280, pp. 1716--1721, 12 June 1998.

....by building CASH as a certifying compiler [23] 6 , we can completely eliminate one complex layer needing verification and testing (the processor) The manufacturing of reconfigurable circuits reuses the same masks for all circuits, reducing cost. As shown by research in the Teramac project [13], reconfigurable hardware architectures can tolerate manufacturing defects through software methods. Only the active SAM is switching at any point, requiring very little power. The SAM implementation uses only local signals. All inter SAM communication is made using a switched, pipelined ....

James R. Heath, Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams. A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology. Science, 280, 1998.

....ASH uses recon gurable hardware devices as a substrate on which the computation is implemented. One important quality of such devices is that parts of the circuit are essentially interchangeable, so a defective part can be replaced by a working one at compile time. Research in the Teramac project [HKSW98] has shown this approach to be viable. To deal with transient errors, we can imagine the synthesis of circuits containing embedded fault tolerance features [Spi96] Certainly, such a solution is also applicable to traditional CMOSbased devices, but the ASH framework may enable the synthesis of ....

James R. Heath, Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams. A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology. Science, 280, 1998.

....and or disguise the input and output channels of the circuit, and the bending and twisting of the individual components in the structures will change their electronic structure so that they no longer behave as desired. A second approach is to intimately couple nano scale hardware with software [21]. One prepares a relatively simple and ordered array of the various components that are needed in the circuit board, such as the switches and wires. Then the complex and logical function is downloaded from some tutor machine onto the resources via a series of electrical signals. This has the ....

J.R. Heath, P.J. Kuekes, G. Snider, and R S. Williams, A Defect Tolerant Computer Architecture: Opportunities for Nanotechnology, Science, 280, 1716, 1998.

....2 One compelling demonstration of this approach is the Hewlett Packard Laboratories Teramac, a massively parallel computer constructed from defective chips, which can recon gure itself and its communication paths to avoid the broken parts and compensate for irregular interconnections. [7] Although Teramac is built from conventional chips, Teramac s disigners view it as a prototype architecture for designing nanoscale computers that would be assembled by chemical processes, where a signi cant fraction of the parts might be defective. 2 In addition to new programming ....

James R. Heath, Philip J. Keukes, Gregory S. Snider, R. Stanley Williams, \A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology," Science, 280 (5370): 1716.

....defects and real time (transient) errors will affect the useful number of devices per unit area. Means for overcoming moderate numbers of permanent chip defects exist for example, by having spare columns on RAM chips [40] or by re routing round defective blocks on field programmable gate arrays [28]. However, it is almost certain that a much more important factor will be transient errors caused by smaller numbers of electrons being associated with each bit of information, by thermal excitation of stray charge carriers, and by background charge variations as carriers are released or trapped ....

.... redundancy for general purpose logic (e.g. 20] 66] 69] 84] The extreme example of how this potential redundancy might be used is the Teramac reconfigurable computer, which is designed to work with only 7 of its FPGAs, 4 of its connections and 7 of its circuit board pathways working [28]. This is an impressive system, but the reader should be aware that the Tera in the machine s name refers to bit operations per second. With only 7 of its 512 chips operational, the Teramac would presumably only be capable of about 200 Mflops, roughly comparable with a single medium sized ....

J.R. Heath, P.J. Kuekes, G.S. Snider & R.S.Williams, "A defect-tolerant computer architecture: opportunities for nanotechnology",Science 280, 1716-1721, 1998

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Heath J.R., P.J. Kuekes, G.S. Snider, and R.S. Williams. 1999. A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology. Science 280:1716-1721.

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James R. Heath, Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams. A defect-tolerant computer architecture: 6 Opportunities for nanotechnology. Science, 280:1716--1721, June 1998.

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James R. Heath, Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams. A defect-tolerant computer architecture: Opportunities for nanotechnology. Science, 280:1716--1721, June 1998.

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J. R. Heath, P. J. Kuekes, G. Snider, and R. S. Williams, "A defect tolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, p. 1717, 1998.

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J. Heath, P. Kuekes, G. Snider, and R. Williams, `A defect tolerant computer architecture: Opportunities for nanotechnology', Science 80 (1998), 1716--1721.

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J. Heath, G. S. P. Kuekes, and R. Williams. A defect tolerant computer architecture: Opportunities for nanotechnology. Science, 80:1716--1721, 1998.

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J. R. Heath et. al., "A defect-tolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, pp. 1716--21, June 1998.

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J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A defecttolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, pp. 1716--1721, 12 June 1998.

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James R. Heath, Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams. A defect-tolerant computer architecture: Opportunities for nanotechnology. Science, 280:1716--1721, June 1998.

No context found.

James R. Heath, Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams. A defect-tolerant computer architecture: Opportunities for nanotechnology. Science, 280:1716-- 1721, June 1998.

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J.R. Heath, P.J. Kuekes, G. Snider, and R.S. Williams, "A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology," Science, vol. 280, pp. 1,716-1,721, 12 June 1998.

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