T. Kalganova and J. F. Miller, "Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness," in 1st NASA/DoD Workshop on Evolvable Hardware, A. Stoica et al., Eds. Los Alamitos, CA: IEEE Computer Society Press, 1999, pp. 54--63.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....an analysis and for retraining. Furthermore, the neurocontrollers may be fully recurrent, as in the agents presented throughout this paper. Pruning algorithms incorporating an explicit network complexity term in the fitness function and performing an evolutionary search have also been suggested [6, 7]. ENM does not rely on such an arbitrarily defined explicit complexity term in the fitness function. It is more akin to variable length encodings algorithms, an example of which is a genetic algorithm with an evolved mask representing the eliminated weights [8] Within ENM, the pruning is based on ....

Kalganova, T., Miller, J.: Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness. In Stoica, A., Lohn, J., Keymeulen, D., eds.: The First NASA/DoD Workshop on Evolvable Hardware, Pasadena, California, IEEE Computer Society (1999) 54-63

....resources were more important than routing. They also noted that the importance of tuning the average number of neighbors to each cell. Kalganova et al. have analyzed how representational biases can affect the geometry both of multiple valued logic netlists [36] and Boolean logic netlists [37]. However all these studies are likely to be dependent on the problem and the other biases employed, making it difficult to draw general conclusions. 3.4.2 Function Level Evolution The function level approach to improving evolvability was developed at ETL, and has been adopted by many others. ....

Kalganova T. and Miller J.F. (1999), Evolving More Efficient Digital Circuits by Allowing Circuit Layout Evolution and Multi-Objective Fitness, Proc. of the 1st NASA/DoD Forkshop on Evolvable Hardware, Pasadena, CA, U.S.A, pp. 54-63.

....in EHW where the circuits tend to grow over time for realizing a given target function. In this paper we present a method for circuit evolution under hardware constraints based on BDDs. The resulting netlists are mapped to MUX based FPGAs. In contrast to previously published approaches (see e.g. (Kalganova Miller, 1999)) we start with a complete description of the function given as a BDD. Assuming that the complete graph does not fit on the FPGA we set an upper limit on the number of MUX cells. This means that the BDD has to be modified to fit on the FPGA. We propose an algorithm based on evolutionary techniques ....

....Nodes from the BDD are removed until the hardware requirements are met. Due to this technique the algorithm runs very fast, i.e. for the first time functions with more than 200 variables can be handled, while other approaches fail for functions with more than 10 variables (Thompson, 1997; Kalganova Miller, 1999). Experimental results are given that demonstrate the trade off between area of the circuit and error introduced. It is shown that our algorithm results in an error of less than 1 on average, if the area is reduced by 20 . 2 Preliminaries 2.1 Binary Decision Diagrams Boolean variables can ....

Kalganova, T., & Miller, J. 1999. Evolving more efficient digital circuits by allowing circuit layout evolution and multiobjective fitness. Pages 54--63 of: NASA/DoD Workshop on Evolvable Hardware.

....of their number of gates) as much as possible. Miller s initial work emphasized generation of functional circuits, rather than optimization. It was not until recently, that Kalganova Miller experimented with a two stage (or multiobjective, as they call it) fitness function as the one used by us [12]. However, the use of truly multiobjective optimization techniques (e.g. based on the concept of Pareto optimality [5] remained as an open area 1 WIRE basically indicates a null operation, or in other words, the absence of gate, and it is used just to keep regularity in the representation used ....

....WIRE basically indicates a null operation, or in other words, the absence of gate, and it is used just to keep regularity in the representation used by the GA that otherwise would have to use variable length strings. of research in combinational circuit design, as suggested by Kalganova Miller [12]. In this paper, we propose the use of an evolutionary multiobjective optimization technique (rather than just a multiobjective fitness function) to design combinational circuits. There is some (relatively scarce) previous work on using multiobjective techniques to handle constraints. This work, ....

[Article contains additional citation context not shown here]

T. Kalganova and J. Miller. Evolving more efficient digital circuits by allowing circuit layout and multi-objective fitness. In A. Stoica, D. Keymeulen, and J. Lohn, editors, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware, pages 54--63, Los Alamitos, California, 1999. IEEE Computer Society Press.

....Kalganova T. et al, 1998 [8] f(2; 1; r) fm (r 1; 1; r) F1 Cartesian GP Multi valued circuit design. Damiani E. et al, 1999 [9] f(4; 1; 2) F1 Conventional GA Hash function design. Aguirre A.H. et al., 1999 [10] fm(3; 1; 2) F1, F2 GP Binary circuit design. Kalganova T. et al., 1999 [11] f(2; 1; 2) fm(3; 1; 2) F1, F2 Cartesian GP Binary circuit design. Masher J. et al, 1999 [12] f(2; 1; 2) F1, F3 Conventional GA Sorting network design. Miller J. 1999 [13] f(2; 1; 2) f(3; 1; 2) F4 Cartesian GP Low pass filter design. Proposed method f(2; 1; r) f(n; m; r) F1, F2 ....

....approach have been investigated in the past. Thus, it has been found that functional set of logic gates [14] as well as circuit layout and connectivity restrictions [8] influence on the GA performance. Some attempts to evolve circuit layout together with circuit functionality have been reported in [11]. A dynamic An Extrinsic Function Level Evolvable Hardware Approach 3 fitness function has been proposed in [11] that allow us to evolve functional complete circuit with minimal number of logic gates employed. In this paper we proposed to use multi input multi output logic functions as logic ....

[Article contains additional citation context not shown here]

Kalganova T. and Miller J. Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness. In Stoica A., Keymeulen D., and Lohn J., editors, Proc. of the First NASA/DoD Workshop on Evolvable Hardware, pages 54--63. IEEE Computer Society, July 1999.

....of logic cells which are in columns to the left of the cell in question. Each logic function describing the behaviour of logic cell is specified in advance. The circuit layout is evolved together with circuit functionality using a rudimentary (1 ) evolutionary strategy with uniform mutation [13], 14] Evaluation of the circuit is carried out using dynamic fitness function that allows us to evolve fully functional circuits as well as reduce their cost in terms of the number of logic gates used [13] 3] 3. Decomposition of Logic Function In order to define the partitioning vectors in ....

.... functionality using a rudimentary (1 ) evolutionary strategy with uniform mutation [13] 14] Evaluation of the circuit is carried out using dynamic fitness function that allows us to evolve fully functional circuits as well as reduce their cost in terms of the number of logic gates used [13], 3] 3. Decomposition of Logic Function In order to define the partitioning vectors in system, some knowledge about its decomposability has to be applied. In this work we will consider both Shannon s and output decompositions. Decomposition means breaking a large logic block into several ....

[Article contains additional citation context not shown here]

Kalganova T. and Miller J. Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness. In Stoica A., Keymeulen D., and Lohn J., editors, Proc. of the First NASA/DoD Workshop on Evolvable Hardware, pages 54--63. IEEE Computer Society, July 1999.

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T. Kalganova and J. F. Miller, "Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness," in 1st NASA/DoD Workshop on Evolvable Hardware, A. Stoica et al., Eds. Los Alamitos, CA: IEEE Computer Society Press, 1999, pp. 54--63.

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