A. Kondratyev, M. Kishinevsky, A Taubin, J. Cortadella, and L. Lavagno. The use of Petri nets for the design and verification of asynchronous circuits and systems. Journal of Circuits, Systems, and Computers, 8(1):67--118, 1998. Home/Search Document Details and Download
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Deadlock And Reachability Checking With Finite Complete Prefixes - Heljanko (1999) (Correct)
....logic program. Our results show that suggested approach is quite competitive when compared to the approaches of McMillan and Melzer Rmer. The main results have been published in [18, 20, 21] The net unfolding approach has also been used for checking properties of speed independent circuits, see [23, 24, 31]. It was also used for model checking a simple branching time logic in [7] see, however, also [16] for a description of a problem with this approach and an approach how to fix it. There is also an algorithm for LTL model checking using prefixes created by Wallner, however, the paper describing an ....
A. Kondratyev, M. Kishinevsky, A Taubin, J. Cortadella, and L. Lavagno. The use of Petri nets for the design and verification of asynchronous circuits and systems. Journal of Circuits, Systems, and Computers, 8(1):67--118, 1998. BIBLIOGRAPHY 68
A Structural Encoding Technique for the Synthesis of.. - Carmona, Cortadella (2002) (4 citations) Self-citation (Cortadella) (Correct)
....a circuit can be derived from an STG. This theory is valid for the class of speed independent circuits, which are correct when assuming that all components of the circuit can have any delay [21] For an STG to be correctly implemented by an speed independent circuit, four conditions must hold [17]: 1. the set of reachable states of must be finite (boundedness) 2. must fulfill the CSC property, 3. function must consistently encode the reachable markings of (consistency) 4. for any pair of signals disables it implies that are input signals (output persistency) ....
Kondratyev, A., Kishinevsky, M., Taubin, A., Cortadella, J., Lavagno, L.: The use of Petri nets for the design and verification of asynchronous circuits and systems, Journal of Circuits Systems and Computers, 8(1), 1998, 67--118.
Behavioral Transformations to Increase Noise Immunity.. - Taubin, Kondratyev.. (1998) Self-citation (Kondratyev Taubin Cortadella Lavagno) (Correct)
....is a boolean function F : B n B such that s 2 S , F #s#=1. 3.2 Behavioral models and Logic Implementability In this subsection we assume the reader to be familiar with Petri nets, a formalism used to specify concurrent systems. We refer to [23] for a general tutorial on Petri nets and to [15] for a review of applications of Petri nets to asynchronous design. 3.2.1 State Graphs A State Graph (SG) is a labeled directed graph whose nodes are called states. Each arc of an SG is labeled with an event, 3 that is a rising (a ) or falling (a, transition of a signal a in the specified ....
....the layout tool and the logic synthesis tool by exchanging information on the relative ease of solving some noise cases by layout or logic. # Most steps of our algorithms (except for the current version of logic synthesis) could be implemented using only STGbased methods (STG unfolding analysis [16, 15]) that are often faster than SG based methods and cope better with the state explosion problem. These techniques, together with the hierarchical approaches mentioned above, would allow us to tackle realistic design problems. 30] pointed out that the digital sensitivity approach has also some ....
A. Kondratyev, M. Kishinevsky, A. Taubin, J. Cortadella, and L. Lavagno. The use of Petri nets for the design andverification of asynchronous circuits and systems. Journal of Circuits, Systems, and Computers, 8(1):67--118, 1998.
Behavioral Transformations to Increase Noise.. - Taubin.. (1998) Self-citation (Kondratyev Taubin Cortadella Lavagno) (Correct)
....is a boolean function F : B n B such that s 2 S , F (s) 1. 3.2 Behavioral models and Logic Implementability In this subsection we assume the reader to be familiar with Petri nets, a formalism used to specify concurrent systems. We refer to [23] for a general tutorial on Petri nets and to [15] for a review of applications of Petri nets to asynchronous design. 3.2.1 State Graphs A State Graph (SG) is a labeled directed graph whose nodes are called states. Each arc of an SG is labeled with an event, 3 that is a rising (a ) or falling (a Gamma) transition of a signal a in the specified ....
....layout tool and the logic synthesis tool by exchanging information on the relative ease of solving some noise cases by layout or logic. ffl Most steps of our algorithms (except for the current version of logic synthesis) could be implemented using only STG based methods (STG unfolding analysis [16, 15]) that are often faster than SG based methods and cope better with the state explosion problem. These techniques, together with the hierarchical approaches mentioned above, would allow us to tackle realistic design problems. 30] pointed out that the digital sensitivity approach has also some ....
A. Kondratyev, M. Kishinevsky, A. Taubin, J. Cortadella, and L. Lavagno. The use of Petri nets for the design and verification of asynchronous circuits and systems. Journal of Circuits, Systems, and Computers, 8(1):67--118, 1998.
Deadlock And Reachability Checking With Finite Complete Prefixes - Heljanko (1999) (Correct)
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A. Kondratyev, M. Kishinevsky, A Taubin, J. Cortadella, and L. Lavagno. The use of Petri nets for the design and verification of asynchronous circuits and systems. Journal of Circuits, Systems, and Computers, 8(1):67--118, 1998.
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