Alex Semenov, Alexandre Yakovlev, Enric Pastor, Marco Pe na, Jordi Cortadella, and Luciano Lavagno. Partial order based approach to synthesis of speed-independent circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 254-265. IEEE Computer Society Press, April 1997. Home/Search Document Details and Download
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Correctness and Reduction in Timed Circuit Analysis - Mercer (2002) (Correct)
....of the level ruled Petri nets to nonstandard designs. These gates are aggressive, and require special analysis to not only synthesize, but to demonstrate correctness. The level ruled Petri net retains enough behaviors from the actual system to make it suitable for this type of analysis. [50, 70] [10, 20] a) b) Fig. 2.11. The net models for the delayed reset domino gate. a) The net to compute f 1 = a b. b) The net to compute f 2 = f 1 c. 35 [500, 500] a t 2 t 1 a [0, 0] 10, 20] a) b) c) Fig. 2.12. Three environment models for the ....
....space for the target submodule and a reduced state space for all things outside of the scope of the target submodule; thus, Property 5.5 holds. Partial order reduction is an important tool in mitigating state explosion in verification [67, 68] Partial order reduction is applied to synthesis in [69, 70]. The 164 approach in [70] is an unfolding technique that is applied to untimed specifications. Not only is it not clear if the technique can be e#ciently applied to a timed model, the technique ignores hierarchy in the specification; thus, it is limited in the size of systems it can be applied ....
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A. Semenov, A. Yakovlev, E. Pastor, M. P. na, J. Cortadella, and L. Lavagno, "Partial order based approach to synthesis of speed-independent circuits," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 254--265, IEEE Computer Society Press, Apr. 1997.
Modular Synthesis of Timed Circuits using Partial Orders on LPNs - Mercer, Myers (2002) (Correct)
....is an alternative circuit model to a timed automaton. It is a transition based specification language where transitions are governed by time and the marked state of the net. Although it is less expressive than timed automata, it is su#cient for not only synthesis but also verification [5,13,25,29,30,23]. Its structure, however, becomes very complicated when modeling even simple logic functions [30] This increases the size of the reachable state space and makes specification di#cult [2] This paper uses level ruled Petri nets (LPNs) which are a hybrid of Petri nets and timed automata. They are ....
....in [2,3] LPNs restrict conflict to the Petri net formalism and facilitate a partial order reduction on the reachable state space. Partial order reduction is an important tool in mitigating state explosion in verification [9,28,15,17,4,19] Partial order reduction is applied to synthesis in [25,31]. The approach in [25] is an unfolding technique that is applied to untimed specifications. Not only is it not clear if the technique can be e#ciently applied to a timed model, the technique ignores hierarchy in the specification; thus, it is limited in the size of systems it can be applied to. ....
[Article contains additional citation context not shown here]
Semenov, A., A. Yakovlev, E Pastor, M. Pe na, J. Cortadella, and L. Lavagno, Partial order based approach to synthesis of speed-independent circuits, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (1997), 254-- 265.
Improved POSET Timing Analysis in Timed Petri Nets - Mercer, Myers (2001) (Correct)
....is required. An # This research is supported by SRC contract 97 DJ 487. other approach is to implicitly store the state space in a directed acyclic graph that is an unfolding of the system. Circuit synthesis is accomplished by approximating and refining covers for segments of the unfolding [9]. However, adding time to unfolding greatly complicates the process yielding an explosion in the number of unfoldings required to capture all behaviors of the system [10] In general, the addition of time to state space exploration exacerbates state explosion. Each state must include a set of ....
A. Semenov, A. Yakovlev, E. Pastor, M. Pena, J. Cortadella, and L. Lavagno. Partial order based approach to synthesis of speed-independent circuits. In Proc. of International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 254--265. IEEE Computer Society Press, April 1997.
Visualisation of Partial Order Models in VLSI Design Flow - Bystrov, Koutny, Yakovlev (2001) Self-citation (Yakovlev) (Correct)
....the iterative process of speci cation re nement. Many aspects of system veri cation (e.g. PN safety, signal consistency, uniqueness of state coding, etc. and some of speci cation correction aspects (e.g. signal insertion to correct state coding problems) can be handled automatically (see, e.g. [3, 10]) However, the convergence of the verify correct cycle is hard to guarantee. Moreover, speci cation correction algorithms use heuristics and often produce a suboptimal solution that is inferior w.r.t. the manually introduced changes. This motivates the design of visualisation tools that allow a ....
Alex Semenov, Alexandre Yakovlev, Enric Pastor, Marco Pe na, Jordi Cortadella, and Luciano Lavagno. Partial order based approach to synthesis of speed-independent circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 254265. IEEE Computer Society Press, April 1997.
Unknown - Modular Synthesis Of (Correct)
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Alex Semenov, Alexandre Yakovlev, Enric Pastor, Marco Pe na, Jordi Cortadella, and Luciano Lavagno. Partial order based approach to synthesis of speed-independent circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 254-265. IEEE Computer Society Press, April 1997.
Modular Synthesis of Timed Circuits using Partial Order.. - Tomohiro Yoneda Eric (2001) (Correct)
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Alex Semenov, Alexandre Yakovlev, Enric Pastor, Marco Pe na, Jordi Cortadella, and Luciano Lavagno. Partial order based approach to synthesis of speedindependent circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 254-265. IEEE Computer Society Press, April 1997.
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