Ilija Had zi c and Jonathan M. Smith. P4: A platform for FPGA implementation of Protocol Boosters. In Field Programmable Logic 1997, number 1304 in Lecture Notes in Computer Science, pages 438--447. Springer-Verlag, 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....technology will be deployed. With current processing and transmission technologies, operating in the control plane will be the short term solution. For the long term, there are potentially interesting schemes for limiting the model of computing ; for example, programmable hardware such as the P4 [HS97] organizes field programmable gate arrays (FPGAs) in a pipeline, allowing processing at 155 Mb s line rates. Other methods of gaining performance include restricting computing operations to a locus within the active packet (for example by examining only headers rather than entire packets ....

Ilija Had zi c and Jonathan M. Smith. P4: A platform for FPGA implementation of Protocol Boosters. In Field Programmable Logic 1997, number 1304 in Lecture Notes in Computer Science, pages 438--447. Springer-Verlag, 1997.

....Networks[3] can subsume protocol adaptation by offering end user programmability of a network infrastructure, but are faced with the same policy issues we address in this paper for the design of any specific solution. We note that protocol adaptation is not limited to software based architectures[8]. We reiterate that the major challenge for any adaptation scheme is the policy decision, that is, when should the protocol graph be reorganized. In a light hearted manner, To boost or not to boost . In this work we provide the common model for making policy decisions and illustrate a proof of ....

....module. A decision submodule must be aware of the time needed to instantiate the new functional module. In the Protocol Boosters model, this time may include module instantiation time for boosters implemented as kernel loadable modules[16] device downloading time for FPGA implemented boosters[8], propagation time over a high latency network, etc. If the event that would trigger the modification of a protocol graph is shorter than the mechanism instantiation time, switching the module in would result in a mismatch between current network conditions and protocol instantiation. This is ....

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I. Hadzi'c and J. M. Smith. P4: A Platform for FPGA Implementation of Protocol Boosters. In Field-Programmable Logic and Applications: 7th International Workshop, FPL'97, Proceedings, LNCS, 1304, pages 438--447. Springer, September 1997.

....in security, performance, usability and flexibility. The intellectually interesting question is whether we can gain some increment in flexibility and still operate in the highest performance regimes. One exploratory effort in this direction is Hadzic s Programmable Protocol Processing Pipeline [HS97] or P4) The P4 consists of four FIFO connected Altera 8000 PLDs with some auxiliary logic. A small crossbar is used to virtualize ordering of operations on the input stream. An input block is used to split ATM cell data from headers, and an output block used to recombine them. The P4 ....

Ilija Had zi c and Jonathan M. Smith. P4: A platform for FPGA implementation of Protocol Boosters. In Field Programmable Logic 1997, number 1304 in Lecture Notes in Computer Science, pages 438--447. Springer-Verlag, 1997.

....protocol specification, interaction between signalling protocol and policy modules and software architecture of current implementation. The purpose of this document is to explain, not to formally specify the SPP4. 1 Overview The SPP4 implementation described in this document runs on P4 platform[HS97] Although this document concentrates on P4 specific implementation, higher level concepts can be generalized to any implementation of Protocol Boosters. Possible extensions of P4 to fully support the Active Network [TSS 97] acceleration is not discussed here. SPP4 consists of three modules. ....

I. Hadzi'c and J. M. Smith. P4: A Platform for FPGA Implementation of Protocol Boosters. In Field-programmable logic and applications: 7th International Workshop, FPL'97, Proceedings, LNCS, 1304, pages 438--447. Springer, September 1997.

....complex that it seems prudent to avoid them unless they are clearly indicated. More simply, if alien were implemented on top of an operating system like Nemesis [LMB 96] it would be possible to use the Flow Manager to demultiplex packets. Additionally, as hardware assisted systems such as P4 [HS97] or U Net [vEBBV95] offer another approach to doing at least some filtering at very high speed. Moreover, the techniques from [WEK96b] or [YBMM94] can provide integrated layer processing. alien could be built on top of any of these techniques. Additionally, the approach of using a small ....

....interface card. In cases where this is not true, their techniques are somewhat more limited, but can provide performance improvements. Additionally, their technique can provide some demultiplexing at the cost of a system call to set it up. A step further in this vein would be to use the P4 [HS97] architecture in combination with Active Networks principles. Because code can be downloaded into the P4, the type of demultiplexing to be performed can be determined at runtime, but still performed at hardware speeds. A final possibility would be to move the language runtime into the kernel ....

Ilija Hadzi'c and Jonathan M. Smith. P4: A platform for FPGA implementation of protocol boosters. In Field Programmable Logic 1997, number 1304 in Lecture Notes in Computer Science, pages 438--447. Springer-Verlag, 1997.

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