BIBLIOGRAPHY 156 #10# James B. Burr. Digital Neurochip Design. In K. Wojtek Przytula and Viktor K. Prasanna, editors, Digital Parallel Implementations of Neural Networks, pages Home/Search Document Details and Download
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Is VLSI Neural Learning Robust against . . . - Card, al. (1994) (Correct)
.... as CMOS circuits requires area efficient implementations of the neurons and synapses, and the use of limited wiring resources [1] These conditions are met by employing, for the arithmetic learning computations, either analog circuits [2] or binary digital circuits of limited precision in bits [3]. It is also possible in the digital case (at low bit precision) to employ stochastic unary arithmetic [4,5] which reflects certain features of the biological neural process including improved fault tolerance. It is not generally known however whether these networks will function properly in view ....
J. Burr, "Digital Neurochip Design," Chapter 8 of Parallel Digital Implementations of Neural Networks, H. W. Przytula and V. K. Prasanna, eds., Englewood Cliffs: Prentice Hall, 1993.
CMOS Area Image Sensors With Pixel Level A/D Conversion - Fowler (1995) (2 citations) (Correct)
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BIBLIOGRAPHY 156 #10# James B. Burr. Digital Neurochip Design. In K. Wojtek Przytula and Viktor K. Prasanna, editors, Digital Parallel Implementations of Neural Networks, pages
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