J. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge, MA, 1985. Home/Search Document Not in Database Summary Related Articles Check |
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Embedded Software in Real-Time Signal Processing.. - Goossens, Van.. (1997) (11 citations) (Correct)
....predict their exact cycle time behavior. 4) Instruction Format: A distinction is made between orthogonal and encoded instruction formats. Anorthogonal format consists of fixed control fields that can be set independently from each other. For example, very long instruction word (VLIW) processors [18] have an orthogonal instruction format. Note that the instruction bits within every control field may additionally have been encoded to reduce the field s width. In the case of an encoded format, the interpretation of the instruction bits as control fields may be different from instruction to ....
....(see Fig. 8) Several techniques have been presented for data routing in compilers for embedded processors. A first approach is to determine the required data routes during the execution of the scheduling algorithm. This approach was first applied in the Bulldog compiler for VLIW machines [18], and subsequently adapted in compilers for embedded processors like the RL compiler [48] and CBC [74] In order to prevent a combinational explosion of the problem, these methods only incorporate local, greedy search techniques to determine data routes. The approach typically lacks the power to ....
J. R. Ellis, Bulldog: A Compiler for VLIW Architectures. Cambridge, MA: MIT Press, 1986.
Speculative Trace Scheduling in VLIW Processors - Manvi Agarwal And (2002) (Correct)
....Tree and (e) Traces of Speculative Trace Scheduling extended basic block scheduling techniques are trace scheduling, superblock scheduling, hyperblock scheduling and decision tree scheduling. The scheduling scopes used in these scheduling schemes are illustrated in figure 1. In trace scheduling [3], compiler picks the most likely path of execution and schedules it for execution. Using a trace, it is possible to expose available ILP because several basic blocks are included in it, which can be scheduled in parallel on the underlying VLIW processor as a single unit. Side entries as well as ....
John R. Ellis, "BULLDOG: A Compiler for VLIW Architectures", ACM Doctoral Dissertation Awards, MIT Press, Cambridge, Massachusettes, 1986.
SUDS: Automatic Parallelization for Raw Processors - Frank (2003) (Correct)
....elimination) to leverage the decomposed interface, rather than forcing the application programmer to do the work. This technique has been used to improve the efficiency of floating point operations [31] fault isolation [122] shared memory coherence checks [100] and memory access serialization [37, 14]. On Raw, micro optimization across decomposed interfaces has been used to improve the efficiency of both branching and message demultiplexing [74] instruction cache tag checks [84, 80] and data cache tag checks [86, 130] Queue conversion micro optimizes by making the renaming of scalar ....
John R. Ellis. Bulldog: A Compiler for VLIW Architecture. PhD thesis, Department of Computer Science, Yale University, February 1985. Technical Report YALEU/DCS/RR-364.
Exploiting Pseudo-schedules to Guide Data.. - Aleta, Codina.. (2002) (2 citations) (Correct)
....[8, 19, 26, 34] All of these studies focused on modulo scheduling algorithms targeting unified (i.e. non partitioned) architectures. A comparison of some of these techniques can be found in [5] There are several works related to acyclic code scheduling for clustered architectures [3, 7, 10, 21, 30]. The most closely related work to our ideas include the work of Kailas, Ebcioglu and Agrawala [22] They proposed an approach to cluster assignment, instruction scheduling and register allocation in a single compilation phase, all based on a list scheduling scheme. The approach taken in [22] ....
J. Ellis. Bulldog: A Compiler for VLIW Architecture. MIT Press, Cambridge, MA, 1986.
Multithreaded Architectural Support for Speculative.. - Processors Manvi Agarwal (Correct)
....of exploiting ILP because of small size of basic blocks. 4 5 interdependent operations on an average in each basic block. In extended basic block scheduling, groups of basic blocks are scheduled as a single unit. Extended basic block scheduling can be categorized into following: trace scheduling [8], superblock scheduling [15] hyperblock scheduling [13] and decision tree scheduling [10] All these scheduling schemes suffer from the drawback of issue slot wastage as explained in [9] In [9] we proposed a new scheduling scheme speculative trcae scheduling for VLIW processors which ensures ....
John R. Ellis, "BULLDOG: A Compiler for VLIW Architectures", ACM Doctoral Dissertation Awards, MIT Press, Cambridge, Massachusettes, 1986.
On the Benefits of Speculative Trace Scheduling in VLIW - Processors Manvi Agarwal (Correct)
....Speculative Trace Scheduling scheduling are: Basic block scheduling and Extended basic block scheduling. The scheduling scopes used in extended basic block scheduling schemes are illustrated in figure 1. Various extended basic block scheduling schemes are elaborated below. In trace scheduling [4], the compiler picks the most likely path of execution and schedules it for execution. Using a trace, it is possible to expose available ILP because several basic blocks are included in it which can be scheduled in parallel on the underlying VLIW processor. Side entries as well as side exits are ....
John R. Ellis, "BULLDOG: A Compiler for VLIW Architectures", PhD thesis, Yale University, 1985.
Non-Local Instruction Scheduling with Limited Code Growth - Keith Cooper Philip (1998) (6 citations) (Correct)
....Restrictions on moving operations between basic blocks are typically encoded in the dpg for the sequence. The first automated global scheduling technique was trace scheduling, originally described by Fisher [8] The technique has been used successfully in several research and industrial compilers [7, 17]. In trace scheduling, the most frequently executed acyclic path through the function is determined using profile information. This trace is treated like a large basic block. A dpg is created for the trace, and the trace is scheduled using a list scheduler. Restrictions on inter block code ....
John R. Ellis. Bulldog: A Compiler for VLIW Architectures. The MIT Press, 1986.
Automatic Synthesis of Customized Local Memories for - Multicluster Application.. (Correct)
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J. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge, MA, 1985.
Modulo Graph Embedding: Mapping Applications onto.. - Park, Fan, Kudlur.. (2006) (Correct)
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J. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge, MA, 1985.
Inducing Heuristics To Decide Whether To Schedule - John Cavazos University (Correct)
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J. R. Ellis. Bulldog: A Compiler for VLIW Architectures. PhD thesis, Yale, Feb. 1985.
Compiler-directed Data Partitioning - For Multicluster Processors (Correct)
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J. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge, MA, 1985.
Automatic Synthesis of Customized Local Memories for.. - Kudlur, Fan, Chu, Mahlke (Correct)
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J. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge, MA, 1985.
Evaluating Register Bank Partitioning with Genetic Algorithms - Dineel Sule Steve (Correct)
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J. R. Ellis. Bulldog: A Compiler for VLIW Architectures. The MIT Press, 1985.
ACRES Architecture and Compilation - Ang, Schlansker (2004) (Correct)
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J.R. Ellis, Bulldog: A Compiler for VLIW Architectures. 1985, Cambridge, Massachussetts: The MIT Press.
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE.. - Nagarajan, etal. (2004) (Correct)
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J. R. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, 1986.
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE.. - Nagarajan, al. (2004) (Correct)
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J. R. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, 1986.
Clustering on the Move - Roos, Corporaal, Lamberts (2002) (1 citation) (Correct)
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J. Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, 1986.
Exploiting Pseudo-schedules to Guide Data.. - Aleta, Codina.. (2002) (2 citations) (Correct)
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J. Ellis. Bulldog: A Compiler for VLIW Architecture. MIT Press, Cambridge, MA, 1986.
Dynamically Reconfigurable Architecture for a Class of Real-Time.. - Ohkami (1992) (Correct)
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J. R. Ellis, Bulldog: A Compiler for VLIW Architectures, The MIT Press, 1986.
Memory Dependence Prediction - Andreas Ioannis Moshovos (Correct)
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J. R. Ellis. Bulldog: A Compiler for a VLIW Architecture. Ph.D. thesis, Yale University, February 1985.
Much Ado about Almost Nothing: - Compilation For Nanocontrollers (Correct)
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J. R. Ellis, Bulldog: A compiler for VLIW Architectures, ACMDoctoral Dissertation Award, MIT Press, 1985.
Graph-Partitioning Based Instruction Scheduling for.. - Aleta, Codina.. (2001) (3 citations) (Correct)
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J. R. Ellis, "Bulldog: A Compiler for VLIW Architectures", MIT Press, pp. 180-184, 1986
Effective Instruction Scheduling with Limited Registers - Chen (2001) (Correct)
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J. R. Ellis. 1986. "Bulldog, A Compiler for VLIW Architectures," MIT Press, Cambridge, MA.
Analysis of Profiling Information for Cache Sensitive Scheduling - Lindenmaier (1999) (Correct)
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John R. Ellis, \Bulldog: A Compiler for VLIW Architectures, ACM Doctoral Dissertation Awards, The MIT Press, 1985
Using Conditional Execution to Exploit Instruction Level.. - Adams, Gray (1995) (Correct)
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J. R. Ellis, Bulldog: A Compiler for VLIW Architectures, The MIT Press, Cambridge, Massachusetts, 1986.
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