Alan J. Hu. Formal hardware verification with BDDs: An introduction. In Pacific Rim Conference on Communications, Computers, and Signal Processing  Home/Search Document Details and Download
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Source-Level Transformations for Improved Formal Verification - Winters (2000) (Correct)
....is that compiler optimizations seek to optimize code execution speed, while we seek to improve the verification code which is to be compiled. Within the formal verification community, a great deal of research has gone into reducing memory usage and runtime (for examples, see some recent surveys [2, 8, 16, 9, 17]) These optimizations are written by experts for experts, optimizing the fundamental verification algorithms in ways that rarely can be expressed in the original language. Obviously, this research is complementary to ours; they optimize models written in a particular style, while we transform ....
Alan J. Hu. Formal hardware verification with BDDs: An introduction. In Pacific Rim Conference on Communications, Computers, and Signal Processing
Verification Methodology for Heterogeneous Hardware/Software .. - Cortes, Eles, Peng (2000) (Correct)
....by BDDs. Firing a transition in a Petri net changes the marking into a new one, which is a variation in the state of the system. It is possible to build the BDD that represents the transition relation of the system and then compute efficiently the reachable G t 4 14 states using BDDs [Bry92] [Hu97]. With such a BDD based representation we can formally verify properties, specified in CTL, using symbolic model checking [Bur94] and accomplish reachability analyses. In our experiments, we use the SMV tool (a BDD based symbolic model checker) SMV] and its input language to describe and verify ....
A. J. Hu, "Formal Hardware Verification with BDDs: An Introduction," in Proc. Pacific Rim Conference on Communications, Computers and Signal Processing, 1997, pp. 677-682.
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