J. Cong, L. He, C.-K. Koh, and P. Madden, "Performance optimization of VLSI interconnect layout," Intergr. VLSI J., vol. 21, no. 1--2, pp. 1--94, Nov. 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....timingdriven Steiner trees. 1. Introduction It is now widely accepted that interconnect is becoming increasingly dominant over transistor and logic performance in the deep submicron regime. Buffer insertion is now a fundamental technology used in modern VLSI design methodologies (see Cong et al. [10] for a survey) Cong [9] illustrates that as gate delays decrease with increasing chip dimensions, the number of buffers required quickly rises. He expects that close to 800,000 buffers will be required for 50 nanometer technologies. It is critical to automate the entire interconnect optimization ....

....sinks into two disjoint clusters and creating separate sub trees for the sinks in each cluster. Notice that it is fairly easy to reduce the wire length in (b) while preserving the topology, which actually yields a self overlapping tree. Existing timing driven Steiner tree constructions (e.g. 5][10][18] cannot find this topology. In general, forming one tree connecting negative sinks and one connecting positive sinks will minimize the number (a) c) critical critical (b) critical (d) critical of buffers but waste wire length. Ideally, one would like to find a tree construction that ....

J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance Optimization of VLSI Interconnect Layout", Integration: the VLSI Journal, 21, 1996, pp. 1-94.

....between two wires, can be minimized. In other words, we do not want adjacent wires to run in parallel for long distances. We assume that , are fixed; we do not consider wire sizing and spacing in our algorithm. But, this can be done as a postprocessing step using a number of techniques (see [28] ad [29] for a comprehensive survey and tutorial) There are two problems introduced by coupling, delay deterioration, and crosstalk. Delay deterioration refers to the fact that the total capacitance seen by a gate is no longer a constant value. The rising contribution of coupling capacitance to ....

J. Cong et al., "Performance optimization of VLSI interconnect layout," Integration, VLSI J., 1996.

....created or old ones deleted. For short wires, an Elmore delay [25] model is used. The wire load capacitances are estimated as lumped capacitances proportional to the Steiner estimates of the lengths of the wires. For longer wires where the RC component is significant, an appropriate delay model [19, 5] is chosen. These models are registered as net delay calculators in an incremental timing analysis engine [10] Both changes to positions of cells and changes to the netlist may trigger incremental recalculations of the timing and Steiner trees. We can have different wire length calculators for ....

J. Cong, L. He, C.-K. Koh, and P. H. Madden. Performance optimization of VLSI interconnect layout. Integration, 21:1--94, 1996.

....and global net routing, it is often imperative to further reduce the delay on global nets to enhance chip performance. Among various interconnect delay optimiza This work is supported by grants from NSF, THECB ATP, and IBM. tion methods, repeater insertion is one of the most effective techniques [8]. There has been considerable previous research in repeater insertion. Van Ginneken [18] proposes a dynamicprogramming based algorithm which finds an optimal repeater placement in a distributed RC tree that gives minimum delay. It has been since then generalized to other applications, for ....

J. Cong, L. He, and C.-K. Koh. Performance Optimization of VLSI Interconnect Layout. In Integration: the VLSI Journal, pages 1--94, 1996.

....a large couphug capacitance. This makes interconnect delay a dominant factor in determining the overall performance [3] Many interconnect performance optimization techniques have been studied extensively, such as topology construction, buffer insertion, driver sizing, wire sizing and spacing (see [4] for a tutorial) Among them, buffer insertion is the most ef fective way to improve interconnect performance. It has been shown that without buffer insertion, the interconnect delay for a wire of length l increases at the rate of O(l 2) without wiresizing, or O(lx ) with optimal wiresizing, but ....

J. Gong, L. He, G.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI Journal, vol. 21, pp. 1-94, 1996.

No context found.

J. Cong, L. He, C.-K. Koh, and P. Madden, "Performance optimization of VLSI interconnect layout," Intergr. VLSI J., vol. 21, no. 1--2, pp. 1--94, Nov. 1996.

No context found.

J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI Journal, vol. 21, pp. 1--94, 1996.

No context found.

J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI Journal, vol. 21, pp. 1--94, 1996.

No context found.

CONG, J., HE, L., KOH, C.-K., AND MADDEN, P. H. 1996. Performance optimization of VLSI interconnect layout. Integration, the VLSI Journal 21, 1--94.

No context found.

J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI Journal, vol. 21, pp. 1--94, 1996.

No context found.

J. Cong, L. He, C. K. Koh, and P. H. Madden, "Performance Optimization of VLSI Interconnect Layout, " Integration, Vol. 21, pp. V$# G , 1996.

No context found.

Jason Cong, Lei He, Cheng-Kok Koh, and Patrick H. Madden. Performance optimization of VLSI interconnect layout. Integration, the VLSI Journal, 21:1--94, 1996.

No context found.

Jason Cong, Lei He, Cheng-Kok Koh, and Patrick H. Madden. Performance optimization of VLSI interconnect layout. Integration, the VLSI Journal, 21:1--94, 1996.

No context found.

J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI Journal, vol. 21, pp. 1--94, 1996.

No context found.

J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI Journal, vol. 21, pp. 1--94, 1996.

No context found.

J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI Journal, vol. 21, pp. 1--94, 1996.

....have begun to play a dominant role in determining system performance, power, reliability and cost. To ensure timing closure of deep submicron designs, it is important to consider the impact of interconnects as early as possible in the design flow. Among the several techniques reviewed in [6], repeater insertion has been found to be one of the most effective methods for optimizing signal delay [12; 9] and slew rate [9] and for minimizing noise [2; 4] Until recently, the option of inserting repeaters was considered only for post placement optimization. Some recent studies [7; 11] ....

J. Cong, L. He, C.-K. Koh, and P. H. Madden. Performance optimization of VLSI interconnect layout. Integration, the VLSI Journal, 21:1--94, 1996.

....has become the dominant factor in determining the overall circuit performance and complexity. To improve the interconnect performance, many interconnect optimization techniques have been proposed recently such as topology construction, driver sizing, buffer insertion, wire sizing, and spacing (see [1] and [2] for a tutorial) Among them, buffer insertion, in particular, is a very effective and useful technique by inserting active devices (buffers) to break original long interconnects into shorter ones so that the overall delay can be reduced. It has been shown that without buffer insertion, ....

J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration VLSI J., vol. 21, pp. 1--94, 1996.

....where the exact geometric layout of all nets is determined. There are two types of derailed routing approaches, grid based or gridless routing. A gridless derailed router allows arbitrary widths and spacings for different nets, which can help to optimize the circuit performance and to reduce noise [10][11] However, the design size that a gridless router can handle is usually limited, due to the high complexity of the routing problem. Since most global routing algorithms run directly on a 2 D or 2.5 D array of routing tiles, such flat approaches may not scale well to large designs. In [12] a ....

J. Cong, L. He, C.-K. Koh, and P. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI journal, vol.21, no. 1-2, pp. 1-94, 1996

No context found.

Cong, J., He, L., Koh, C.-K. and Madden, P.H. (1996) Performance Optimization of VLSI Interconnect Layout. Integration, the VLSI Journal, 21 (1). 1-94.

No context found.

J. Cong, L. He, C.-K. Koh and P. H. Madden, "Performance Optimization of VLSI Interconnect Layout", Integration 21 (1996), pp. 1--94.

No context found.

J. Cong, L. He, C.-K. Koh and P.H. Madden, "Performance optimization of VLSI interconnect layout", Integration 21 (1996), pp. 1--94.

No context found.

J. Cong, L. He, C.-K. Koh and P. H. Madden, "Performance optimization of VLSI interconnect layout", Integration 21 (1996), pp. 1-94.

No context found.

Cong, J., He, L., Koh, C.-K. and Madden, P.H. (1996) Performance Optimization of VLSI Interconnect Layout. Integration, the VLSI Journal, 21 (1). 1-94.

No context found.

J. Cong, L. He, C. K. Koh, and P. Madden, "Performance optimization of vlsi interconnect layout," Integration, the VLSI Journal, pp. vol. 21, pp. 1--94, 1996.

First 50 documents  Next 50

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC