D. Cherepacha, D.M. Lewis, "DP-FPGA: An FPGA Architecture Optimized for Datapath", in VLSI Design, vol. 4, no. 4, pp. 329-343, 1996.  Home/Search   Document Not in Database   Summary   Related Articles

....fast long distant communication busses. It should be noted that, in this case, we are in the same conditions as in multi FPGA systems: the design has to be partitioned between areas of logic cells. Datapath implementation is also an intensive field of research. The DP FPGA proposed by Cherepacha [5] is an architecture in which all functional units are composed of a 4 input 4 output lookup table (LUT) a fast carry chain and an output latch. This architecture is well suited for applications requiring intensive arithmetic calculation on large numbers. The main drawback is that control logic ....

D. Cherepacha, D.M. Lewis, "DP-FPGA: An FPGA Architecture Optimized for Datapath", in VLSI Design, vol. 4, no. 4, pp. 329-343, 1996.

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