Robert Heaton, Donald Blevins, and Edward Davis. A Bit-Serial VLSI Array Processing Chip for Image Procesing. IEEE Journal of Solid-State Circuits, 25(2):364--368, April 1994. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Reconfigurable Architectures and General-Purpose Computing in the.. - DeHon (1996) (Correct)
....Note #131 August 2, 1996 Year Design Organization Size 2 area cycle ALU bit ops 2 s 1987 DEC MP [Gro87] 32 Theta4 10.4mm Theta9.4 mm 1 98M 100 ns 13 1990 MP1 [Nic90] 32 Theta4 11.6mm Theta9.5mm 0.8 170M 70 ns 11 1990 SLAP [FHR94] 4 Theta16 7.9mm Theta9.2mm 1 73M 100 ns 8. 8 1990 BLITZEN [HBD94] 128 Theta1 11mm Theta11.7mm 0.5 514M 50 ns 5 1993 MP2 [KT93] 32 Theta32 14mm Theta14mm 0.5 780M 80 ns 16 1994 IMAP [YKF 94] 64 Theta8 15.5mm Theta15.6mm 0.28 3G 25 ns 6.6 1995 MIT Abacus 1000 PEs 6.5mm Theta7.3mm 0.5 190M 8 ns 660 [BSV 95] 2 3 LUTs PE) 1995 MGAP 2 [GOI95] 2 Theta2 ....
....ALU Bit Ops= 2 s = W d Theta N PE Area 2 Theta P fraction Theta t cycle Table 15: Survey of SIMD Processor Capacity Year Design F density I density D desnsity 1987 DEC MP [Gro87] 13 0 3.4 Theta10 Gamma4 1990 MP1 [Nic90] 11 0 2.4 Theta10 Gamma4 1990 SLAP [FHR94] 8. 8 0 1990 BLITZEN [HBD94] 5 0 2.5 Theta10 Gamma4 1993 MP2 [KT93] 5.4 0 5.2 Theta10 Gamma5 1994 IMAP [YKF 94] 6.6 0 6.7 Theta10 Gamma4 1995 MIT Abacus [BSV 95] 660 0 3.0 Theta10 Gamma4 1995 MGAP 2 [GOI95] 160 0 2.6 Theta10 Gamma5 1996 Sony [KHN 96] 38 7.4 Theta10 Gamma7 2.0 Theta10 Gamma4 ....
Robert Heaton, Donald Blevins, and Edward Davis. A Bit-Serial VLSI Array Processing Chip for Image Procesing. IEEE Journal of Solid-State Circuits, 25(2):364--368, April 1994.
Building Microelectronic Systems In A University Environment - Poulton (1991) (1 citation) (Correct)
....and Wayne Dettloff of MCNC [14] The board plugs into a Sun host and can perform 580,000 inferences (flips) per second. It was delivered to Oak Ridge National Laboratory, where it is used in a robotics application. The Blitzen project is based on million transistor custom chips designed at MCNC [9]. The chips, 5 which contain 128 bit serial SIMD processors, can be used to configure very large Xmesh connected arrays. Eight chips are mounted on a Sun compatible board, designed and built by Raj Singh of our laboratory. The board has been delivered to NASAGoddard, where it is being used to ....
Heaton, R., Blevins, D., and Davis, E., "A Bit-Serial VLSI Array Processing Chip for Image Processing," IEEE JSSC, Vol. 25, No. 2, pp. 364-368, 1990.
Reconfigurable Architectures for General-Purpose Computing - DeHon (1996) (55 citations) (Correct)
....processing element 44 Year Design Organization Size 2 area cycle ALU bit ops 2 s 1987 DEC MP [Gro87] 32 Theta4 10.4mm Theta9.4 mm 1 98M 100 ns 13 1990 MP1 [Nic90] 32 Theta4 11.6mm Theta9.5mm 0.8 170M 70 ns 11 1990 SLAP [FHR94] 4 Theta16 7.9mm Theta9.2mm 1 73M 100 ns 8. 8 1990 BLITZEN [HBD94] 128 Theta1 11mm Theta11.7mm 0.5 514M 50 ns 5 1993 MP2 [KT93] 32 Theta32 14mm Theta14mm 0.5 780M 80 ns 16 1994 IMAP [YKF 94] 64 Theta8 15.5mm Theta15.6mm 0.28 3G 25 ns 6.6 1995 MIT Abacus 1000 PEs 6.5mm Theta7.3mm 0.5 190M 8 ns 660 [BSV 95] 2 3 LUTs PE) 1995 MGAP 2 [GOI95] 2 Theta2 ....
....Bit Ops= 2 s = W d Theta N PE Area 2 Theta P fraction Theta t cycle Table 4.15: Survey of SIMD Processor Capacity Year Design F density I density D desnsity 1987 DEC MP [Gro87] 13 0 3.4 Theta10 Gamma4 1990 MP1 [Nic90] 11 0 2.4 Theta10 Gamma4 1990 SLAP [FHR94] 8. 8 0 1990 BLITZEN [HBD94] 5 0 2.5 Theta10 Gamma4 1993 MP2 [KT93] 5.4 0 5.2 Theta10 Gamma5 1994 IMAP [YKF 94] 6.6 0 6.7 Theta10 Gamma4 1995 MIT Abacus [BSV 95] 660 0 3.0 Theta10 Gamma4 1995 MGAP 2 [GOI95] 160 0 2.6 Theta10 Gamma5 1996 Sony [KHN 96] 38 7.4 Theta10 Gamma7 2.0 Theta10 Gamma4 ....
Robert Heaton, Donald Blevins, and Edward Davis. A Bit-Serial VLSI Array Processing Chip for Image Procesing. IEEE Journal of Solid-State Circuits,25(2):364-- 368, April 1994.
System Design for a Computational-RAM Logic-In-Memory.. - Nyasulu (1999) (Correct)
....that makes data access from the nearest neighbors implicit in the architecture. Examples of such hardware inter PE communications include the 2 D (North, East, West, and South neighbors) connectivity used in MIT Pixel Processor [14] the square or X (nearest 8 neighbors) connectivity of BLITZEN [72], and other more complicated networks such as the hypercube and the global router used in the Connection Machine [73] and MasPar MP1 [29] Fora3x3neighborhood, data can be accessed from a neighbor PE in at most two cycles for the 2 D inter PE connectivity, and one cycle for the square ....
Robert Heaton, Donald Blevins, and Edward Davis, "A Bit-Serial VLSI Array Processing Chip for Image Processing", IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, April, 1990.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC