R. Torrance, et al, "A 33 GB/s 13.4 Mb Integrated Graphics Accelerator and Frame Buffer", IEEE International Solid-State Circuits Conference, pp 340-341, February, 156 1998.  Home/Search   Document Not in Database   Summary   Related Articles

....would have eight add multiply units running at 1000 MHz and sixteen 1 Kbit buses running at 50 MHz, resulting in system performance of 16 Gflops and 100 GB s. Figure 2.9 Organization of an IRAM Vector Processor 2.2. 5 An Integrated Graphics Accelerator and Frame Buffer This is a commercial chip [18] designed by Mosaid and Accelerix using some ideas from early CRAM research work [3] The 33 GB s, 13.4 Mb chip integrates parts of the graphics processor with DRAM. Other on chip units include a PCI interface, VGA core Level One Instruction Cache Level One Data Cache Net Interface Two Way, ....

....implemented on the same chip Introduction 35 (see Chapter 8) Therefore, to maintain the small additional area of CRAM over standard RAM, the controller must use as few gates as possible. Also, since a combined RAM logic system will generally mean logic being implemented in a slow RAM process [9] [18], a simple controller would yield higher speed. High PE Utilization: One of the underlying requirement of an SIMD PE controller is to make sure that the PEs are always kept busy. In other words, instructions to the PEs must be issued fast enough to match the rate at which the PEs execute them. ....

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R. Torrance, et al, "A 33 GB/s 13.4 Mb Integrated Graphics Accelerator and Frame Buffer", IEEE International Solid-State Circuits Conference, pp 340-341, February, 156 1998.

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