A. H. Timmer, M. J. M. Heijligers, and J. A. G. Jess, "Fast System-Level Area-Delay Curve Prediction," Proc. 1st APCHDL, pp. 198-207, 1993.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....area and delay. This approach, however, constrains the designer to explore a fraction of the design space. Furthermore, the accuracy of the estimators was not reported. There is some recent work on estimating lower bounds on area cost and total control steps (or csteps) 4] 5] 6] [7], and [8] are mainly concerned with FUs in their area cost models. 9] 10] 11] 12] and [13] use more elaborate cost function for estimation. However, they do not consider both: 1) dependencies among different types of resources, and (2) linkage to physical level. By contrast, our approach ....

A. H. Timmer, M. J. M. Heijligers, and J. A. G. Jess, "Fast System-Level Area-Delay Curve Prediction," Proc. 1st APCHDL, pp. 198-207, 1993.

....accurate estimates of design quality when large behavioral descriptions are partitioned onto several chips, without the need of running HLS tools to obtain full design netlists. 2 Previous Work There is some recent work for estimating lower bounds on area cost and total control steps (or csteps) [3, 4, 5, 6, 7, 8, 9, 10, 11, 12]. All of these works (with the exception of [7] 10] 11] and [12] are mainly concerned with FUs in their area cost models. The work in [3] proposes a mathematical model for predicting the area delay curve. 4] proposes an ILP formulation for lower bound estimation of performance given ....

....The work in [3] proposes a mathematical model for predicting the area delay curve. 4] proposes an ILP formulation for lower bound estimation of performance given resource constraints. 5] addresses lower bounds on time and FU cost for functional pipelined data flow graph, but not register cost. [6] also addresses lower bounds on time and FU cost. It uses these two estimation algorithms to predict system level area delay curve. However, it does not feature register cost estimation, either. An extension of the work in [3] is described in [7] and addresses lower bounds on time and area cost ....

A. H. Timmer, M. J. M. Heijligers, and J. A. G. Jess, "Fast System-Level Area-Delay Curve Prediction," Proc. 1st APCHDL, pp. 198-207, 1993.

....estimates on the total area cost of hardware resources. Section 9 presents experimental results on several HLS benchmarks. Section 10 concludes with a summary. 2 Previous Work Some of the recent work on estimating lower bounds on area cost and total control steps (or csteps) is described in [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14]. All of these works (with the exception of [5] 12] 13] and [14] are mainly concerned with FUs in their area cost models. The work in [4] proposes a mathematical model for predicting the area delay curve. An extension of this work is described in [5] and addresses lower bounds on time and ....

....cost including interconnect cost, but not register cost. 6] proposes an ILP formulation for lower bound estimation of performance given resource constraints. 7] addresses lower bounds on time and FU cost for a functional pipelined data flow graph, but neither register cost nor interconnect cost. [9] also addresses lower bounds on time and FU cost. It uses these two estimation algorithms to predict the system level area delay curve. However, it does not consider register and interconnect cost in estimation. 10] presents a formal approach which seems to estimate FU cost better than [5] and ....

A. H. Timmer, M. J. M. Heijligers, and J. A. G. Jess, "Fast System-Level Area-Delay Curve Prediction," Proc. 1st APCHDL, pp. 198-207, 1993.

....constraints. BEC 94 Baltic Electronics Conference The 4th Biennial Conference on Electronics and Microsystems Technology. Tallinn, Estonia, October 9 14, 1994, pp. 391 396. 2 Most of the estimation functions used today are predefined and based on one of the following principles [3] 4] 5] 8][14]: In a problem analysis a closed form of expression is derived which is either a heuristic formula or an upper or lower bound. A probabilistic distribution is derived in a statistical analysis. Recently, the tentative construction of a netlist or a floorplan has been proposed for ....

A.Timmer, M.Heijligers, J.Jess. "Fast System-Level Area-Delay Curve Prediction". Proc. 1st Asian Pacific Conf. on HDL, Stand. & Appl., IEEE, December 1993, pp.198-207.

....or latency) Finding the optimal tradeoff curve between these two metrics is called design space exploration. Design space exploration is generally considered too difficult to solve optimally in a reasonable amount of time, so the problem is usually limited to computing either lower bounds [3] or estimates [4] on the optimal tradeoff curve for some set of time or resource constraints. Moreover, the design space is usually determined by solving only the scheduling and functional unit allocation subproblems. The design space exploration methodology described here goes beyond traditional ....

....other time constraint could be replaced by the smaller of the two time constraints that it would lie between without any increase in area. As a simple example, consider the design space exploration problem for the DIFFEQ example [7] using library A from Table 1 (Timmer s trivial library 1 from [3]) and a clock length of 100. The minimum time 1 Note that, although we are solving only the TCS problem, this methodology is not limited to solving only that problem, and could be extended to include register allocation, interconnect allocation, control unit design, etc. MODULE AREA DELAY (ns) ....

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A. H. Timmer, M. J. M. Heijiligers, and J. A. G. Jess, "Fast System-Level Area-Delay Curve Prediction," in Proc. of 1st APCHDLSA, pp. 198--207, 1993.

....components of the BSG s [Dulm63] Edges not belonging to these components cannot be part of any complete matching, so they can be removed without excluding any feasible schedule. Such a removal can reduce the incident OEI, because an OEI cannot be larger than the union of adjacent MEI s. In [Timm93c] it was shown that both the BSG s and the irreducible components can be determined in O( V 2 ) If a removal leads to the reduction of an OEI, a new run of the algorithm can be started to reduce the OEI s even more. The union of all OEI s contains O( C # V ) cycles, so the number of runs is ....

.... a time and resource constrained scheduling problem, by deriving either a lower cycle bound [Timm93b] or a module set with lower bound area [Timm93a] If a lower bound turns out to be infeasible or no schedule can be found with the approach of section 5, the next cycle bound or the next module set [Timm93c] is derived, until a feasible set of time and resource constraints is found. We have compared our scheduling approach with the IP scheduling approach based on node packing [Gebo92] Both approaches are implemented in C using the synthesis interface of the NEAT system [Heij94] Both approaches ....

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A.H. Timmer, M.J.M. Heijligers and J.A.G. Jess, "Fast System--Level Area--Delay Curve Prediction", Proc. APCHDLSA, pp. 198--207, Brisbane (Aus), 1993.

....is used to avoid random search by subtracting a lower bound of the completion time from the completion time of the resulting schedule. An accurate lower bound of the completion time using precedence relations and resource constraint information can be calculated using the method reported in [Timm93a]. 1000 1500 2000 2500 3000 3500 4000 0 50 100 150 200 250 300 350 400 cost #iterations Genetic Algorithm Results average min Figure 1: Convergence of genetic scheduling, fdct, 2 multipliers, 2 adders The genetic parameters have been determined empirically, however changing these parameters within ....

A.H. TIMMER, M.J.M. HEIJLIGERS, AND J.A.G. JESS. Fast System-Level Area-Delay Curve Prediction. In first Asia Pacific Conference on Hardware Description Languages, Standards and Applications, pages 198--207, Brisbane (Australia), December 1993.

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A. H. Timmer, M. J. M. Heijiligers, and J. A. G. Jess, "Fast System-Level Area-Delay Curve Prediction," in Proc. of 1st APCHDLSA, pp. 198--207, 1993.

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