D. A. Patterson. Reduced instruction set computers. Commun. ACM, 28(1):8--21, 1985.  Home/Search   Document Not in Database   Summary   ACM   TOC   Related Articles   Check

....that our approach is compatible with static tools. For example, one might use FX 32 to statically translate from the x86 instruction set to the Alpha instruction set and then run the resulting binary on a SEA. Finally, we note that sofware extended architectures represents an application of RISC [Pat85] philosophy. While RISC pushed hardware complexity into software, an SEA allows new hardware functionality to be implemented in software. 3 Software extended architectures The key component of a software extended architecture is the dynamic instruction translator. In this section, we describe ....

D. A. Patterson. Reduced instruction set computers. Communications of the ACM, 28(1):8-21, January 1985.

....comparison of our network processor benchmark with a workstation benchmark shows this in Chapter 3) For the processing engine of our router, we consider RISC cores, VLIW processors, DSPs, and specialized co processors. Reduced Instruction Set Computers Reduced Instruction Set Computers (RISC) Pat85] were proposed in the 1980 s as an alternative to increasingly complex Complex Instruction Set Computers (CISC) RISC architectures are typically relatively simple (several dozen to few hundred instruction, orthogonal addressing modes, etc. pipelined, and supported by a sophisticated ....

David A. Patterson. Reduced instruction set computers. Communications of the ACM, 28(1):8--21, January 1985.

....device, verification could be performed off line, along with highly optimizing compilation. In this case, the function of the Java specialization layer is being performed at compile time rather than at run time. It is possible to draw an analogy with the introduction of RISC microprocessors [Pat85] over the last decade as with the design of the JVM, some of the most baroque CISC processors were burdened with features to close the semantic gap between assemblyand high level programming. When these processors were used to support different languages, or when new compiler optimization ....

David A. Patterson. Reduced instruction set computers. Communications of the ACM, 28(1):8--21, January 1985.

....fetch and decode process is lengthened by a variable length format, the clock cycle time might need to be increased, or additional pipeline stages might need to be added. These effects have performance costs that could easily offset any gain due to increased code density. According to Patterson [60], processing time overhead for even the simple scheme investigated for the Stanford MIPS machine was too high; it was believed that it added 10 percent to the MIPS cycle time, and the feature was abandoned. To justify the complications of a variable length format, a significant performance ....

....to using a register windowing scheme. Register windows provide a sliding window type access to a large register file, which can be used by procedure call, for example, to reduce memory traffic in saving and restoring non volatile scratch registers. This scheme was used in the Berkeley RISC machine [60], as well as the Am29000 [42] and SPARC [27] Link time register allocation, which allows static allocation of registers across procedure calls [79] has been shown to perform as well or better than register windows, and partitioning the register file and dedicating several registers to globals ....

David A. Patterson. Reduced instruction set computers. CACM, 28(1), January 1985.

....interconnects were done manually in the basic cells. The full design consists of about 120 000 transistors. Introduction The RISC versus CISC debate during the past decade resulted in a lot of improvements to the microprocessor industry and finally RISC dominated the majority of the designs [1, 2]. Another factor that helped also in this improvement was the introduction of more powerful and easy to use CAD tools. It was thus thought that undergraduate students should begin designing and implementing such architectures using available CAD s. The objective was to produce a RISC processor ....

....easy to use CAD tools. It was thus thought that undergraduate students should begin designing and implementing such architectures using available CAD s. The objective was to produce a RISC processor with comparable characteristics to those already built by researchers in universities in the past [2]. The design is done using the OCEAN CAD tools available from Delft university in the Netherlands where the final chip is to be fabricated. This affected the choice of architecture since the packaging allows 32 pins only. Therefore a reduced architecture was implemented, while a more powerful one ....

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D.A. Patterson, "Reduced Instruction Set Computers",Communications of the ACM, vol. 28, No. 1, Jan. 1985, pp 8--21.

....stored in a read only memory) 2.1 On embedded processor programming The field of machine level code generation is not homogeneous. The generalpurpose Reduced Instruction Set Computer (RISC) processors are specifically designed to be programmed with optimizing high level language compilers [80]: for instance, global register allocation [19] is straightforward due to the large uniform register file. But especially in the embedded real time computing area, there are many special purpose processor architectures that must often programmed in assembly language (which is not an easy task ....

D. A. Patterson. Reduced instruction set computers. Communications of the ACM, vol. 28, no. 1, pp. 8--21. January 1985.

....that our approach is compatible with static tools. For example, one might use FX 32 to statically translate from the x86 instruction set to the Alpha instruction set and then run the resulting binary on a SEA. Finally, we note that sofware extended architectures represents an application of RISC [Pat85] philosophy. While RISC pushed hardware complexity into software, an SEA allows new hardware functionality to be implemented in software. 3 Software extended architectures The key component of a software extended architecture is the dynamic instruction translator. In this section, we describe ....

D. A. Patterson. Reduced instruction set computers. Communications of the ACM, 28(1):8--21, January 1985.

....is a good measure of complexity because it is independent of system load, clock speed, or other architecture dependent parameters. On common RISC processors, instructions that reference memory tend to be more expensive than pure register operations, because memories are slower than processors [Pat85] Likewise, branches are disruptive because they interrupt instruction pipelines. Therefore, in our tables of complexity, we indicate not just the number of instructions, but also the number of memory references and whether or not a branch is involved. The statistics reported are from the SPARC ....

David Patterson. Reduced Instruction Set Computers. Communications of the ACM, 28(1):8--21, 1985.

.... INTRODUCTION In the last two decades, the performance of single CPU microprocessors has increased enormously, mostly due to continuing improvements in computer architecture [Rau and Fisher 1993] One major architectural breakthrough has been the RISC (Reduced Instruction Set Computer) technology [Patterson 1985] based on instruction pipelining which overlaps execution steps of different instructions, Authors addresses: S. M. Moon, School of Electrical Engineering, Seoul National University, Seoul 151 742, Korea; email: smoon altair.snu.ac.kr; K. Ebcioglu, IBM T. J. Watson Research Center, P.O. Box 218, ....

Patterson, D. 1985. Reduced instruction set computers. Commun. ACM 28, 1 (Jan.), 8--21.

....merge point is forced to become an m out ofn code. This means that every branch merge point will be verified for correct control transfer. However, forcing a verification point requires a compensating instruction at every branch point [13] This problem is solved in [12] by using the delay slot [17] available in many modern processors. With this arrangement, there will not be any significant performance degra dation of the main processor due to the compensating instructions. 3.1 Analysis Definition 1: A signature verification point (SVP) is a location in the code where the signature ....

D. Patterson, "Reduced instruction set computers, " CACM, vol. 28, pp. 8 -- 21, January 1985.

....always possible to increase the speedup produced by an optimizer by generating worse unoptimized code. Another factor that has to be taken into account is the effect of the architecture. Some machines are easier to generate code for than others. One of the arguments in favor of the RISC movement [Patt85] was that a simple architecture makes it easier to write better optimizers, as the number of combinations to consider is significantly smaller. An attempt to evaluate the effect of optimization on different architectures using again the Uopt optimizer is reported in [Cude89] This study found that ....

Patterson, D.A., "Reduced Instructions Set Computers", Comm of the ACM, Vol.28, No.1, January 1985, pp. 8-21.

....used instructions and adding instructions that decreased path lengths without contributing significantly to the cost of implementation. Appendix A lists the full instruction set of Concurro. The final outcomes of these trade offs give the Concurro ISA many characteristics that Patterson [Patt85] has ascribed to RISC architectures: fixed length instructions with predominantly simple semantics, register register operations facilitating pipelining, and memory accesses through load and store instructions. 2.1.1 Execution Model Concurro is a multiple context processor, with each ....

D.A. Patterson, "Reduced instruction set computers," Commun. ACM , vol. 28, no. 1, pp. 76--89, Jan. 1985.

....is evident; big computer companies like IBM, Hewlett Packard, and Digital have also embraced the concept. The RISC approach promises many advantages over Complex Instruction Set Computer, or CISC, architectures, including superior performance, design simplicity, rapid development time, and others [19, 22]. Studying all of these factors at once is beyond the scope of this paper, which will on leave from Digital Equipment Corp. 1990 91. look only at performance, and in fact only at performance from the architectural perspective. That is, we will try to control for all influences on performance ....

Patterson, D.A. Reduced Instruction Set Computers. Comm. ACM 28, 1 (Jan. 1985), pp. 8-21.

....even at the assembly language level. Do we really need to bother much about the peculiarities of assembly languages Is it not so that RISC type microprocessors are speci cally designed to be programmed with optimizing high level language compilers The answer to the latter question is yes [19], of course, but there are also many important special purpose processors for which no compiler available seems to be good enough. Typically, such processors are used in embedded real time computing systems: representative examples can be found among digital signal processors (DSPs) 14] In many ....

D. A. Patterson. Reduced instruction set computers. Communications of the ACM, vol. 28, no. 1, pp. 821. January 1985.

....important to remember that a solution that takes fewer clock cycles but requires significantly more complicated hardware may actually take more real time to execute than a simpler scheme with less complicated hardware. This is, in fact, the basic argument behind reduced instruction set processors [Patt85]. 3.1. The Simulator The simulator used in this study was a modified version of the PIPE simulator, which was written to facilitate the study of the PIPE processor [Farr89] The PIPE processor, a single chip processor designed and built at the University of Wisconsin, is an outgrowth of the ....

D. A. Patterson, "Reduced Instruction Set Computers", Communications of the ACM, vol. 28, no. 1 (January 1985), pp. 8-21.

....virtual dispatch table, the INNER dispatch table, etc. The do part is represented as a list of bytecodes for an architecture independent language: Alpha. The Alpha code is a low level architecture independent representation of MetaBETA do parts. It has the following properties: Close to RISC [Patterson 85] It is possible to quickly generate e#cient code for contemporary microprocessor architectures. BETA specific. Complex actions, such as object invocation, INNER calls and attribute assignment are represented as one operation. Minimal. A few number of general operations to make the code ....

D. Patterson. Reduced Instruction Set Computers. CACM, 28(1), January 1985.

....procedures in a data dependent manner. Each procedure activation requires a small amount of run time state for local variables. While some of this local state may reside in memory, the rest occupies the processor s register file. The register file is a critical resource in most modern processors [34,66]. Operating on local data in registers rather than memory speeds access to that data, and allows a short instruction to access several operands [75,28] There have been many proposals for hardware and software mechanisms to manage the register file and to efficiently switch between activations ....

....registers in hardware, spilling and restoring variables as needed. This added flexibility can significantly improve the performance of many sequential and parallel programs. Table 2 2 shows a similar comparison between a conventional register file, the NamedState Register File, register windows [31,66], and the C machine stack cache [25,11] A windowed register file selects registers within the current active window, much like a segmented register file. It also manages register window frames for sequential programs with a combination of hardware support and runtime trap handlers [14] Several ....

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David A. Patterson. "Reduced instruction set computers." Communications of the ACM, 28(1):8--21, January 1985.

....Reading it today, one would never guess this landmark paper was written more than 40 years ago, as most of the architectural concepts seen in modern computers are described there. For an account of the principles of modern general purpose sequential (i.e. von Neumann) computer design, see e.g. [119, 120, 208]. For sequential computation, the stability of the von Neumann model has permitted the development, over the last three decades, of a variety of high level languages and compilers. These have, in turn, encouraged the development of a large and diverse software industry producing portable ....

....which need to be addressed in the future in order to continue the development of this framework for general purpose parallel computing based on fine grain concurrency in a shared address space. 6.1. Architecture Most distributed memory architectures are based on conventional microprocessors [119, 120, 208]. We need alternative processor designs which can support a very large number of lightweight threads simultaneously, and can provide fast context switching, message handling, address translation, hashing etc. 44, 69, 71, 130, 274] If such designs are not produced then we may find that the ....

D A Patterson. Reduced instruction set computers. Communications of the ACM, 28(1):8-- 21, January 1985.

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D. A. Patterson. Reduced instruction set computers. Commun. ACM, 28(1):8--21, 1985.

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D. A. Patterson. Reduced instruction set computers. Commun. ACM, 28(1):8--21, 1985.

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D. A. Patterson, "Reduced Instruction Set Computers," Communications of the ACM, Vol.28, No.1, Janurary 1985, pp.8--21.

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David A. Patterson. Reduced Instruction Set Computers. Communications of the ACM 28 (1): 8-21, January 1985.

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David A. Patterson. Reduced Instruction Set Computers. Communications of the ACM 28 (1): 8-21, January 1985.

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Patterson, D. A. Reduced Instruction Set Computers, Communications of the ACM, Vol#28, No#1 (January#1985), pp#8-21.

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Patterson, D. A. Reduced Instruction Set Computers, Communications of the ACM, Vol#28, No#1 (January#1985), pp#8-21.

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