F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....of the whole system than procedural realtime systems. Most scheduling algorithms assume that the WCET estimation of each task is known prior to doing the schedulability analysis. Typically, the WCET analysis and schedulability analysis are carried out separately. Sophisticated techniques [6, 16, 17, 19], are used in WCET analysis, for instance to model caching and pipelining, to achieve safe and tight WCET estimation. However, most WCET analysis approaches are only considered in relation to procedural programming languages. Performing WCET analysis on objectoriented programs must take into ....

F. Mueller. Static Cache Simulation and its Applications. Ph.d thesis, Department of Computer Science, Florida State University, July 1994.

....by defining appropriate iblock replacement functions in the cache model. Then, thanks to abstract cache states values, each iblock within a basic block is classified in one of the four following categories: always hit, always miss, first miss and conflict. The interested reader may refer to [13] for a detailed classification description. always hit: the iblock reference always results in a cache hit. always miss: the iblock reference always results in a cache miss (it is the most pessimistic case) first miss: the first reference of the iblock results in cache miss and cache hit ....

F. Mueller. Static Cache Simulation and its Application. PhD thesis, Departement of Computer Sciences, Florida State University, July 1994.

....Dependent Machine Configurations Data Cache Data Caching Categorizations Linker Simulation Results Library Simulator EASE Figure 2.1: Overview of Bounding Data Cache Performance 6 7 each data reference in the program. This static stimulation is based on previous work described in [19]. The timing analyzer reads machine dependent information to determine how each instruction proceeds through the pipeline. It uses the data categorizations to determine whether each data reference should be treated as a hit or miss during the pipeline analysis. The timing analyzer also uses the ....

....graph is analyzed to determine the possible data lines that can be in the data cache at the entry and exit of each basic block within the program. Static simulation in general and its particular use in the simulation of caches for instruction categorization is explored in detail by Mueller in [19]. The iterative algorithm used for static instruction cache simulation [3, 19] will not be sufficient for static data cache simulation. The problem is that the calculated references can access a range of possible addresses. At the point that the data access occurs, the data lines associated with ....

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F. Mueller. Static Cache Simulation and its Applications. PhD dissertation, Dept. of Computer Science, Florida State University, July 1994.

....account the effect of instruction cache, pipeline and branch prediction when computing the WCETs of portions of code have been specified. The presence of pipelines is tackled by simulating the flow of instructions in the pipelines. Considering the instruction cache uses static cache simulation [10]: every instruction should be classified according to its worst case behavior with respect to the instruction cache. The instruction classification process uses both the program syntax tree and the control flow graph. A similar approach is used to integrate the effect of branch prediction (see [4] ....

.... to achieve WCET analysis: characterizing the possible execution paths, and computing the execution time of a given execution path in an accurate and safe manner by considering the hardware state (hardware level execution time analysis) Studied architectural features are pipelines [17, 7] caches [9, 10], and branch prediction [4] Most published results on WCET analysis were experimented on small benchmark programs. We are not aware of any use of WCET analysis on the code of large applications (except [5] which is described below) In particular, to our knowledge, no prior study has dealt with ....

F. Mueller. Static Cache Simulation and its Application. PhD thesis, Departement of Computer Sciences, Florida State University, July 1994.

....and branch prediction when computing programs wcets. Pipeline. The presence of pipelines is considered by simulating the flow of instructions in the pipelines, in a method similar to the one proposed in [1] Instruction cache. Consideration of instruction cache uses static cache simulation [2]: every instruction is classified according to its worst case behavior with respect to the instruction cache. The instruction classification process uses both the program syntax tree and control flow graph. Branch prediction. An approach similar to the one used for the instruction cache was ....

F. Mueller. Static Cache Simulation and its Application. PhD thesis, Departement of Computer Sciences, Florida State University, July 1994.

....performance for a particular design. One difficulty with trace driven simulation is the expense of gathering traces. vpo supports the efficient gathering and analysis of traces [WHAL93] Note: Details to be included in full paper. We also describe vpo s use in developing hard real time systems[ARNO94, MUEL94]. 12 5 Related Work Auslander and Hopkins describe the implementation of the PL.8 compiler [AUSL82] The PL.8 code improver employed phase iteration, and the authors also noted that this greatly simplified the implementation of the various code improving transformations. While the PL.8 ....

Mueller, F., Static Cache Simulation and Its Application, Ph.D. Dissertation, Florida State University, August 1994.

.... with different methods (see [PK89, LMW95] However, cache memories and pipelines in modern microprocessors complicate the determination of the execution time of a single (machine) instruction, as this time depends on the execution path that leads to it (see [FMW97, AFMW96, BN94, LBJ 95, Mue94, MWH94] Although it is safe to count every memory access of an instruction as a cache miss, this strategy overestimates the execution time significantly 1 . In the following, we will present a pre runtime, nonpreemptive scheduling method that takes the cache behavior into account. Its WCET ....

F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Florida State University, July 1994.

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F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

....loop bodies only require a few traversals to bound the WCET for the entire loop. We capture the worst case behavior of architectural components along execution paths and compose these paths for loops, functions, and, ultimately, the entire application, to derive cycle counts that bound the WCET [1,2,11,23,24,25,26,27,38,39,40]. Figure 1 shows the organization of the timing analysis environment, which has been adapted to model the VISA and the Simplescalar instruction set (PISA) 6] The application is compiled to assembly code using the gcc PISA compiler. Control flow and instruction data memory references are ....

....upper bounds on the number of iterations for loops are provided. FIGURE 1. Static timing analysis toolset. A static cache simulator uses the control flow information to construct a control flow graph of the program that consists of the call graph and the control flow graph of each function [2,23]. The program s control flow graph is Prediction Timing Cache Categorization VISA Specification Gcc (PISA) Compiler Source Files Simulator Cache Static Control Flow I D References Analyzer then analyzed, and caching categorizations are derived for each instruction and data ....

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F. Mueller. Static Cache Simulation and its Applications. Ph.D. Thesis, Dept. of CS, Florida State Univ., July 1994.

....interaction from the user. This work provides the means to bound the WCET for instruction caches with arbitrary levels of associativity. It is based on prior work with the group at Florida 2 State University, which included bounding the instruction cache performance for direct mapped cache [25, 22, 3, 11] and later extensions for set associate caches [23, 32] In addition to the prior work, this paper speci es a data ow framework that describes the problem of cache prediction, also xes some problems in the instruction categorizations for set associative caches and provides a number of examples ....

....It di ers, on the other hand, since the simulation environment does not perform actual inlining through code duplication. Recursive calls require special treatment. Since our overall framework does not support recursion at the time, we omit the details in this paper as they can be found elsewhere [22]. The next section describes how caches can be simulated by interprocedural analysis. 4. Static Cache Simulation The method of static cache simulation provides the means to predict the caching behavior of instruction and data references. The following sections formalize the handling of ....

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F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

.... instance, an upper bound on the number of loop iterations has to be known, indirect calls should not be used, and memory should not be allocated dynamically [39] Often, recursive functions are also not allowed, although there exist outlines on treating bounded recursion similar to bounded loops [28]. Our static analysis framework handles call and return sequences by distinguishing the instances of functions, which differ for different calling sequences of the same function. This approach covers non recursive programs. Recursive programs require a distinction between the first and any ....

F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

....instance graph which uniquely identifies each function instance by the sequence of call sites required for its invocation. This program control flow graph is analyzed to determine the possible data lines that can be in the data cache at the entry and exit of each basic block within the program [19]. The iterative algorithm used for static instruction cache simulation [2, 19] is not sufficient for static data cache simulation. The problem is that the calculated references can access a range of possible addresses. At the point that the data access occurs, the data lines associated with these ....

....sequence of call sites required for its invocation. This program control flow graph is analyzed to determine the possible data lines that can be in the data cache at the entry and exit of each basic block within the program [19] The iterative algorithm used for static instruction cache simulation [2, 19] is not sufficient for static data cache simulation. The problem is that the calculated references can access a range of possible addresses. At the point that the data access occurs, the data lines associated with these addresses may or may not be brought in cache, depending upon how many ....

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F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

....instance graph, which uniquely identifies each function instance by the sequence of call sites required for its invocation. This program controlflow graph is analyzed to determine the possible data lines that can be in the data cache at the entry and exit of each basic block within the program [13]. The iterative algorithm used for static instruction cache simulation [2, 13] is not sufficient for static data (a) Detecting Spacial Locality int a[100] 100] int a[100] 100] main( row order sum main( column order sum int i, j, sum = 0; int i, j, sum = 0; for (i = 0; i ....

....sequence of call sites required for its invocation. This program controlflow graph is analyzed to determine the possible data lines that can be in the data cache at the entry and exit of each basic block within the program [13] The iterative algorithm used for static instruction cache simulation [2, 13] is not sufficient for static data (a) Detecting Spacial Locality int a[100] 100] int a[100] 100] main( row order sum main( column order sum int i, j, sum = 0; int i, j, sum = 0; for (i = 0; i 100; i ) for (j = 0; j 100; j ) for (j = 0; j 100; j ) for (i = 0; i ....

F. Mueller. Static Cache Simulation and its Applications. PhD dissertation, Dept. of Computer Science, Florida State University, July 1994.

....for code instrumentation (rather than inserting measurement code in every basic block) The resulting directed graph of UPs represents the control flow of the program in such a form that it can be easily processed later by the static cache simulator. A formal definition of UPs is given in [11, 12]. A path macro invocation is generated on a unique transition of each UP in the assembly code. The corresponding body of the macro, which provides the measurement code for the UP, is defined by the static cache simulator. Similarly, a call macro invocation is generated for each call to a function. ....

....associated with the UPs. Such an abstract cache state specifies the possible cache contents before the UP is executed. First, formal definitions are provided. Then, the caching behavior of each instruction is categorized based on these definitions. An example is discussed in section 4. 3 (see [11] for more details) In Proceedings of the 28th Annual Simulation Symposium, April 1995 Definition 1 A program line can potentially be cached if there exists a sequence of transitions in the combined control flow graphs and call graph (with function instances) such that the program line is cached ....

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F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

....PowerPC 604 8 PowerPC 620 Table 1: Associativity of Caches for various Processors The work presented here goes one step beyond the previous research by introducing the first framework to handle WCET prediction for set associative caches. Generalizing the work of static cache simulation [15] of direct mapped caches to set associative caches, a formalization of the new method is given and the operational characteristics are presented and discussed by example. Furthermore, WCET predictions for several programs are presented by combining the static cache analysis for set associative ....

.... the WCET, an upper bound on the number of loop iterations has to be known, indirect calls should not be used, and memory should not be allocated dynamically [20] Often, recursive functions are also not allowed, although there exist outlines on treating bounded recursion similar to bounded loops [15]. In particular in the presence of caches, non preemptive scheduling is assumed to prevent undeterministic behavior due to unpredictable context switch points. If context switches occurred at arbitrary points (e.g. in a preemptive system) cache invalidations may occur resulting in unexpected ....

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F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

....[22, 14, 8] and from uncached architectures to direct mapped instruction caches [3, 13, 11] The work presented here goes one step beyond the previous research by introducing the first framework to handle WCET prediction for set associative caches. Generalizing the work of static cache simulation [16] of direct mapped caches to set associative caches, a formalization of the new method is given and the operational characteristics are presented and discussed by example. Furthermore, WCET predictions for several programs are presented by combining the static cache analysis for set associative ....

.... the WCET, an upper bound on the number of loop iterations has to be known, indirect calls should not be used, and memory should not be allocated dynamically [20] Often, recursive functions are also not allowed, although there exist outlines on treating bounded recursion similar to bounded loops [16]. In particular in the presence of caches, non preemptive scheduling is assumed to prevent undeterministic behavior due to unpredictable context switch points. If context switches occurred at arbitrary points (e.g. in a preemptive system) cache invalidations may occur resulting in unexpected ....

[Article contains additional citation context not shown here]

F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

....reduce the amount of instrumentation code inserted into a program for on the fly analysis. It can also be used to enable a program timing tool to take the effects of caching into account. A more comprehensive overview of static cache simulation including further applications can be found elsewhere [8]. 2 Control Flow and Call Graph Analysis In this section, terms and methods are introduced to analyze the call graph of a program and the control flow graphs of each function. The analysis is performed to find a small set of measurement points suitable for on the fly analysis. The analysis ....

....vertices as visited during the depth first traversal. If an already visited edge is encountered again, the last edge in the current traversal is due to recursion. The depth first search will then backtrack and retain this backedge as a special edge in the function instance graph (see algorithm in [8]) Example 4. In Figure 3, function f contains three calls: a call to g and two calls to h. Function g calls i and k. Function h calls k. Function i calls g, which is an indirect recursive call. The corresponding function instance graph contains two instances of h (for each call from f0) and ....

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F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

.... instance, an upper bound on the number of loop iterations has to be known, indirect calls should not be used, and memory should not be allocated dynamically [25] Often, recursive functions are also not allowed, although there exist outlines on treating bounded recursion similar to bounded loops [19]. Recent research in the area of predicting the WCET of programs has made a number of advances. Conventional methods for static analysis have been extended from unoptimized programs on simple CISC processors to optimized programs on pipelined RISC processors, and from uncached architectures to ....

F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

....[LL73] This is also reflected in the increasing number of preemptive real time operating systems [GL91, Hil92] These systems are available for a number of cached processors. Recently, it has been shown that tight predictions of the WCET of programs can be obtained even for cached systems [AMWH94, Mue94]. These results were obtained under the assumption that tasks be scheduled non preemptively. This paper discusses how these results can be generalized for preemptive systems via cache partitioning. For an existing architecture, the cache space can be divided into partitions, each of which are only ....

....the response time after context switches will improve since cached code data of a task will remain in memory across context switches. This is an important asset for real time applications. 3 In addition, the predictability gained by cache partitioning allows the use of static cache simulation[Mue94] to determine the worst case execution time[AMWH94] and perform schedulability analysis in conventional cached systems that are preemptively scheduled. Notice that the timing analysis has to take into account that processor pipelines are flushed on context switches, potentially inflicting wait ....

F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

....of the WCET, an upper bound on the number of loop iterations has to be known, indirect calls should not be used, and memory should not be allocated dynamically. Often, recursive functions are also not allowed, although there exist outlines on treating bounded recursion similar to bounded loops [11]. Early work in the field of WCET prediction used a timing schema to propagate execution times of programming structures along the control flow graph of functions and call graph of a program. Park analyzed programs at the source level (disregarding compiler optimizations) 12] while Harmon et al. ....

....compared to up to seconds with our approach) it seems questionable if this approach is feasible when used every day in the software development cycle. It is not clear how their approach scales in general with changing associativity. An alternate formalization based on our instruction categories [11] is presented for set associative caches via abstract interpretation [2] but no results have been reported. They used our notion of abstract cache states but their method distinguishes a may analysis (using set unions of cache states at joins in the control flow) and a must analysis (using set ....

F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

....counting to track always hits, always misses, and first misses. It also includes local state transitions similar to a finite state automaton to determine at execution time whether a conflict results in a cache hit or a cache miss. The details of static cache simulation can be found elsewhere [12, 10, 9]. Our prior work dealt with an ideal RISC processor that exhibits a single cycle overhead for an instruction execution on a cache hit and a constant overhead for a cache miss (estimated at 10 cycles) Our current work concentrates on applying the hardware simulation to an existing processor and ....

F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

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F. Mueller. Static Cache Simulation and its Applications. Ph.d thesis, Department of Computer Science, Florida State University, July 1994.

No context found.

F. Mueller. Static Cache Simulation and its Applications. PhD thesis, Dept. of CS, Florida State University, July 1994.

No context found.

Mueller, F. (1994) Static Cache Simulations and its Applications. PhD Thesis, Department of Computer Science, Florida State.

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