Q. Yu and E. S. Kuh, "Exact moment matching model of transmission lines and application to interconnect delay estimation," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 3, pp. 311--322, June 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....time but di#erent shift times) Therefore some potential non inferior waveforms can be removed by this pruning process. Furthermore, the lumped circuit approximation presented in [1, 12] is not as accurate as the transmission line model or simulations based on SPICE especially in high frequency [17]. In this paper, we present a graph based algorithm for optimal bu#er insertion under accurate delay models. In our algorithm, a signal is accurately represented by a finite ramp which is characterized by two parameters, shift time and transition time. Any accurate delay model, such as delay ....

....Model Input (S, T) Output (S, T) Figure 2. a) A wire connecting two bu#ers. b) Signal waveform calculation is cascaded in terms of a pair (S, T ) We use the transmission model to model the interconnect wire, which is found more accurate than methods based on lumped circuit approximation [9, 17]. Under the transmission line model, voltage and current at any position are described by the telegraph s equations. In modeling the interconnect wire, we take both fringing capacitance and inductance into consideration. Both e#ects are found important in today s design [3, 8] The waveform ....

Q. Yu and E.S. Kuh, Exact Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation, IEEE Trans. on VLSI, Vol.3, No.2, pp.311-322, 1995.

....pin keeps increasing as the switch size rises. This effect can be explained considering that as the switch size rises the load seen by the buffer is larger because there is a better connection to the subsequent load capacitors. 3. Experimental Results As pointed out recently by Yu and Ku [5], transmission lines models are necessary for long paths and or fast digital circuits. The convenience of doing so has been checked out after some HSPICE simulations with a single RC stage, a 20 stage distributed RC cascadated quadrupole like the ones studied by [3] and a lossless transmission ....

Qingjian Yu and Ernest S. Kuh, "Exact Moment Matching Model of Transmission Lines and Aplication to Interconnect Delay Estimation", IEEE Transactions on VLSI, Vol. 3, N. 2, June 1995.

....in achieving high performance circuits. Techniques aiming at reducing interconnect delay are highly desirable. Buffer insertion is an efficient technique in interconnect optimization. It has been an active research area in the past few years, resulting in a large body of literature on the subject [1, 2, 4, 6, 7, 14, 17, 19, 21]. Traditionally, buffer insertion is a post layout optimization technique, meaning that it is applied to improve the layout after the routing stage. Recently, it was demonstrated in [22] that simultaneous routing and buffer insertion can produce significantly better results, and an algorithm based ....

....2: a) A buffer to buffer segment showing a wire connecting two buffers. b) Signal waveform calculation is cascaded in terms of a pair (#, # ) We use the transmission line model to model the interconnect wire, which is found to be more accurate than methods based on lumped circuit approximation [10, 21]. Under the transmission line model, voltage and current at any position are described by the telegraph equations. In modeling the interconnect wire, both fringing capacitance and inductance, considered important in today s design [3, 9] are taken into consideration. The waveform calculation for ....

Q. Yu and E.S. Kuh, Exact Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation, IEEE Trans. on VLSI, Vol.3, No.2, pp.311-322, 1995.

....as follows: t t s 0 s i 36 4m 2 66 3 m 2 if 4m 90 (2) where m j i is the j th order moment of the voltage transfer function of node i. Moments of an RLC interconnect can be computed by the methods proposed in [33, 20]. In this paper, we present a new approach to moment computation in Section 4. Signal response waveform is another important factor in interconnect design. Under ideal situations, one would prefer the transmission of the input signal to the output not to be distorted. However, due to impedance ....

....moments of sinks in a topology in an incremental fashion, exploiting the fact that the interconnect structure changes only slightly from an iteration to the next in the RATS tree algorithm. 4 Incremental Bottom Up Moment Computation Moments can be computed by the polynomial time algorithms in [33, 20]. However, these works compute moments by traversing the entire tree iteratively, and do not allow incremental computation of moments as the tree topology changes. As a result, when the topology changes during routing tree construction, another round of iterative tree traversals is needed to ....

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Q. Yu and E. S. Kuh. Exact moment matching model of transmission lines and application to interconnect delay estimation. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 3(2):311--322, June 1995.

.... 2( m 1 ) 2 m 2 ) p 3(m 1 i ) 2 4m 2 if 4m 2 i 3(m 1 i ) 2 0 3:90 m 1 i 2 if 4m 2 i 3(m 1 i ) 2 = 0 ; 2) where m j i is the j th order moment of the voltage transfer function of node i. Moments of an RLC interconnect can be computed by the methods proposed in [33, 20]. In this paper, we present a new approach to moment computation in Section 4. Signal response waveform is another important factor in interconnect design. Under ideal situations, one would prefer the transmission of the input signal to the output not to be distorted. However, due to impedance ....

....moments of sinks in a topology in an incremental fashion, exploiting the fact that the interconnect structure changes only slightly from an iteration to the next in the RATS tree algorithm. 4 Incremental Bottom Up Moment Computation Moments can be computed by the polynomial time algorithms in [33, 20]. However, these works compute moments by traversing the entire tree iteratively, and do not allow incremental computation of moments as the tree topology changes. As a result, when the topology changes during routing tree construction, another round of iterative tree traversals is needed to ....

[Article contains additional citation context not shown here]

Q. Yu and E. S. Kuh. Exact moment matching model of transmission lines and application to interconnect delay estimation. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 3(2):311--322, June 1995.

.... b k of the transfer function for the general RLY circuit of Figure 8 can be obtained using the recursion equation given in [6] The first and second 11 Our model is not limited to traditional segment models, and accuracy of our results would likely improve if we use non uniform segment models [6, 16] designed to perfectly match the low order moments of the distributed RLC line. coefficients of the transfer function are b SL 1 = R S N X j=1 Y 1;j RN N X j=1 Y 1;j b N 1 b SL 2 = R S N X j=1 Y 1;j Delta b j 1 R S N X j=1 Y 2;j RN N X j=1 Y 1;j Delta b j 1 ....

Q. Yu and E. S. Kuh, "Exact Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation", IEEE Trans. VLSI Systems 3, June 1995, pp. 311-322.

....an RLY equivalent circuit. Only two admittance moments need to be computed for an exact transfer function moment computation for the main path. The k th 6 Our model is not limited to traditional segment models, and accuracy of our results would likely improve if we use non uniform segment models [7, 19] designed to perfectly match the low order moments of the distributed RLC line. Y N R 1 V 1 Y 1 L C 1 V L L N R L N R S S V V N N 1 Figure 6: Representation of the main path in the tree, where each distributed line is modeled using RLC segments. Y i indicates the off path subtree admittance at ....

Q. Yu and E. S. Kuh, "Exact MomentMatching Model of Transmission Lines and Application to Interconnect Delay Estimation", IEEE Trans. VLSI Systems 3, June 1995, pp. 311-322.

.... (11) and (12) We also compute the delay at the given sink node using SPICE3e, where each edge of the tree is modeled using the LTRA 6 Our model is not limited to traditional segment models, and indeed we believe the accuracy of our results would improve if we use non uniform segment models [5, 18] designed to perfectly match the low order moments of the distributed RLC line. DO NOT PROPAGATE this draft or information contained within Interconnect Driver Load SPICE Elmore New Model parameters res. cap. Delay Delay Delay m Omega pF ps ps ps R = 0:015 Omega C = 0:176 fF 10 ....

Q. Yu and E. S. Kuh, "Exact Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation", IEEE Trans. VLSI Systems 3, June 1995, pp. 311-322.

....derived from Gerzberg s model) 2 The concept of non uniform equivalent circuits has also been used in other areas, e.g. O Brien et al. 14] and Gopal et al. 7] obtain non uniform segment models for driving point impedance at a gate output using moment matching techniques. Recently Yu et al. [32] have also proposed a method, different from what we propose below, for deriving models by directly matching the moments of the transfer function. However, we note that their models are inaccurate as the complete set of constraints for the moment matching model are not considered. We simulate ....

....circuit. Therefore, by using 2k Gamma 1 Pi segments we can exactly match the total 4k Gamma 1 constraints. Also 2k Gamma 1 L segments equivalent circuit can be used but will generate overspecified system of equations [13] Here, we note that the constraints generated using Yu and Kuh s method [32] are not complete, as they do not consider the constraints corresponding to the load term are not considered. We note that this could be the reason for the different model parameters in the second order moment matching model (see Figure 9) So it can be concluded that open ended models derived ....

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Q. Yu and E. S. Kuh, "Exact Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation", IEEE Trans. VLSI Systems, 1995, pp. 311-322.

....H i (s) Z 0 h i (t)e Gammast dt = j=0 ( Gamma1) j j s j Z 0 t j h i (t)dt = j=0 ( Gamma1) j Delta m j i Delta s j : 1) where m j i is the j th moment of the transfer function. Moments of an RLC interconnect can be computed by the methods proposed in [20, 21]. From the first 2q Gamma 1 moments, one can construct a q pole transfer function H (s) to approximate the actual transfer function H i (s) as follows: H i (s) q j=1 k s Gamma p j ; 2) where p j s are poles and k j s are residues, all of which can be determined uniquely by ....

....the higher order moments and evaluate the sink delays and signal quality for each wiresizing solution. We present an incremental bottom up moment computation algorithm in the following. 3. 5 Incremental Bottom Up Moment Computation Moments can be computed by the polynomial time algorithms in [20, 21]. However, these works compute moments by traversing the entire tree iteratively, and do not allow incremental computation of moments. As the topology changes, another round of iterative tree traversals is needed to re compute the moments. Even when we restrict the topology change to a simple ....

[Article contains additional citation context not shown here]

Q. Yu and E. S. Kuh, "Exact moment matching model of transmission lines and application to interconnect delay estimation," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 3, pp. 311--322, June 1995.

.... Delta Delta Delta. Several approaches have been proposed to compute the moments at each node of a lumped RLC tree, where the lumped resistors and lumped inductors are floating from the ground and form a tree, and the lumped capacitors are connected between the nodes on the tree and the ground [KaMu95, RaPi94, YuKu95b]. In the following, we present a method proposed by Yu and Kuh [YuKu95b] for moment computation in an RLC tree. Consider a lumped RLC tree with n nodes. Let k be the parent node of node k, and T k be the subtree rooted at node k. Let C k be the capacitance connected to node k, R k and L k be the ....

.... each node of a lumped RLC tree, where the lumped resistors and lumped inductors are floating from the ground and form a tree, and the lumped capacitors are connected between the nodes on the tree and the ground [KaMu95, RaPi94, YuKu95b] In the following, we present a method proposed by Yu and Kuh [YuKu95b] for moment computation in an RLC tree. Consider a lumped RLC tree with n nodes. Let k be the parent node of node k, and T k be the subtree rooted at node k. Let C k be the capacitance connected to node k, R k and L k be the resistance and inductance of the branch between k and k. Let H k (s) V k ....

[Article contains additional citation context not shown here]

Q. Yu and E. S. Kuh "Exact Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 3(2), Jun. 1995, pp. 311--322.

.... and the moment matching method have been successfully used for the delay estimation, model order reduction and interconnect optimization [1] These tasks can be very efficiently implemented as there are explicit formulas and a linear order algorithm for the moment computation of such RC trees [2]. In today s deep submicron technology, due to the dense placement of the interconnect wires and the large aspect ratio of wire height over wire width, the coupling capacitance between two wires may be even larger than the ground capacitance of each wire and can never be neglected. In this case, ....

....father node, then the computation complexity is , as the number of s grows linearly with the order. However, if discrete model is used to represent each RC line as used in RICE [11] if for each line there are sections in the model, then the computation cost will be . It has been shown [2] that in order to get exact moment matching by a nonuniform discrete model, and it is often seen in the literature, e.g. in [12] that a large number of uniform RC sections are used to model a line and the number of sections is proportional to the length of the line, but in our algorithm ....

Q.Yu & E.S.Kuh, "Exact moment matching model of transmission lines and application to interconnect delay estimation," IEEE Trans. on VLSI Sys., vol.3, pp.311-322, June 1995.

....integration with the time complexity O(p 4 ) for a pth order model, which is costly for high order computation. Also, this method is good for interconnects modeled as transmission line trees, but its extension to more general interconnect topology has not been shown. In our recent paper [27], we presented a lumped model for moments of a resistortransmission line capacitor (R T C) network. When the transmission lines are replaced by their p th order moment matching model, the network is transformed into a lumped RLC network such that the two networks have identical moments up to order ....

Q.Yu and E.S.Kuh, "Exact moment matching model of transmission lines and application to interconnect delay estimation," to be appeared on IEEE Trans. on VLSI systems.

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Q. Yu and E. S. Kuh, "Exact moment matching model of transmission lines and application to interconnect delay estimation," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 3, pp. 311--322, June 1995.

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Q. Yu and E. S. Kuh. Exact moment matching model of transmission lines and application to interconnect delay estimation. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 3(2):311--322, June 1995.

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