J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance " for the RC interconnect of CMOS gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 1526--1535, Dec. 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of the paper we assume that PMOS and NMOS have the same driving capability. Therefore it is not necessary to distinguish between rising transition and falling transition. Because of the resistance shielding, the load capacitance in the # factor equations is the effective capacitance for the wire [18]. To compute the effective capacitance, we use analytical expressions to calculate the input admittance # ###.We expand # ### into Taylor series and keep first three terms, i.e. # ### # ### # ### # ### . The technique in [16] is applied to determine an equivalent CRC # model which matches ....

....# ###.We expand # ### into Taylor series and keep first three terms, i.e. # ### # ### # ### # ### . The technique in [16] is applied to determine an equivalent CRC # model which matches # ###. Then, we compute the effective capacitance # ### for this CRC # model using the technique in [18]. For our delay model, we note that shift time # is additive. That is, if an input waveform #### ### causes an output waveform ####### ####, then another input waveform ###### ## # will cause an output waveform #### # ###### ####. For the buffer macro model in equations (1 2) the additivity of ....

J. Qian, S. Pullela and L. Pillage, Modeling the "Effective Capacitance" for the RC Interconnect of CMOS Gates, IEEE Trans. on Computer-Aided Design, Vol.13, No.12, pp.15261535, 1994.

....current conveyors, IEEE Trans. Circuits Syst. I, vol. 46, pp. 1364 1365, 1999. 6] M. T. Abuelma atti and H. A. Al Zaher, New universal filter with one input and five outputs using current feedback amplifiers, Analog Integrated Circuits and Signal Processing, vol. 16, pp. 239 244, 1998. [7] Z. J. Lata and P. B. Aronhime, Cascadable current mode biquads, Analog Integrated Circuits and Signal Processing, vol. 13, pp. 275 284, 1997. 8] A. Fabre and M. Alami, Universal current mode biquad implemented from two second generation current conveyors, IEEE Trans. Circuits Syst. I, vol. ....

....in different ways [1] An expression for the propagation delay when a load is modeled simply by a resistor in series with a capacitor was derived in [6] However, the driving transistor was considered to operate always in linear mode and only the simplified case of step input was examined. In [7], the RC output load was replaced by an effective capacitance, which was calculated by an iteration procedure based on simplified assumptions for the shape of the output response. The real output waveform was approximated by the charging discharging of the effective capacitance up to a point and ....

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J. Qian, S. Pullela, and L. Pillage, "Modeling the "effective capacitance" for the RC interconnect of CMOS gates," IEEE Trans. Computer-Aided Design, vol. 13, no. 12, pp. 1526--1535, Dec. 1994.

....Imaging Systems, and by grants from Xerox Corporation, IBM Corporation, Intel Corporation, Lucent Technologies Corporation, and Eastman Kodak Company. derstanding of the device and circuit behavior when operating within the deep submicrometer region. The propagation delay model based on [15] and [16] is not physically intuitive, which involves curve fitting techniques and does not explicitly consider the device parameters. The MOS transistors are modeled as a linear resistor in [10] neglecting the nonlinear behavior of the MOS transistors. In this paper, an extension of previous ....

....characterizing the propagation delay of both fast and slow ramp input signals are presented. The output voltage of a CMOS inverter is based on a fast ramp input signal. The interconnect resistance shields the load capacitance in the saturation region as compared to a purely capacitive load [15]. The signal quality is also degraded by the interconnect resistance, causing additional short circuit power to be dissipated by the following logic stage. The accuracy of these analytic equations is compared with SPICE simulations. The waveform of the estimated output voltage based on these ....

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J. Qian, S. Pullela, and L. Pillage, "Modeling the "Effective Capacitance" for the RC Interconnect of CMOS Gates," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-13, No. 12, pp. 1526--1535, December 1994.

....complexity under the extended device model. The posynomial program formulation for the simultaneous gate and wire sizing problem [9] was also extended to accommodate a voltage ramp gate model, which considers the impacts of the input switching time and output loading under the C eff model [14]. The resulting sizing problem, however, is no longer a posynomial program. It is unknown how far away the solution obtained by solving a posynomial program is from the exact solution under and spacing. Our extracted capacitance values closely match those given in the NTRS (see [1] IEEE ....

....total table size is 5 Theta3 Theta5 Thetam = 75m, where m is the number of gate types. Satisfactory optimization results are obtained according to experiments in Section III D. For simplicity, we assume that c l is the lumped capacitance in this paper. Extension to the effective capacitance model [14] is ongoing work and will be discussed briefly in Section V. Theorem 3: The STIS problem under the STL bounded device model is a general CH program. Note that the STL bounded model might not be monotonic with respect to the sizing solution X. Therefore, the STIS problem is unlikely a ....

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J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance" for the RC interconnect of CMOS gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 1526--1535, Dec. 1994.

....one data entry of the arrival time for each signal delay is obtained. Steps 1 through 3 represent cell interconnect delay estimation. Step 1 determines the effective load capacitance seen by the current cell output. Any of the previously published methods can be used to obtain this capacitance [10, 8]. Step 2 represents computation of the signal arrival time and transition time for all inputs to the given cell and interconnect delay analysis. The interconnect RC delay can be derived using any of the known methods (e.g. 11] Given the output loading obtained in Step 1 and the input ....

J. Qian, S. Pullela, and L. Pillage. Modeling The "Effective Capacitance " for The RC Interconnect of CMOS Gates. IEEE Trans. on CAD, 13(12):1526--1535, Dec. 1994.

....delay is computed by multiplying the effective resistance with the total capacitance. Another commonly used driver delay model pre characterizes the driver delay of each type of drivers in terms of the input transition time t , and the total load capacitance C L in the form of k factor equations [30, 29], such as: t d f = k 1 k 2 Delta C L ) Delta t t k 3 Delta C 3 L k 4 Delta C L k 5 ; 8) t f = k 0 1 k 0 2 Delta C L ) Delta t t k 0 3 Delta C 2 L k 0 4 Delta C L k 0 5 ; 9) where k 1 Delta Delta Delta5 and k 0 1 Delta Delta Delta5 are determined based on ....

....new value of the effective capacitance is computed using Eqn. 11) and it is used as the loading capacitance for the next iteration of computation. The process stops when the value of C e f f does not change in two successive iterations. A so called resistance model (R model) was also proposed in [29] to better approximate the slow decaying tail portion of the response waveform. This method illustrates the complication of the interaction between the drive model and the interconnect model in the deep submicron design. III. DEVICE LAYOUT OPTIMIZATION In this section, we discuss the ....

J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "Effective Capacitance " for the RC Interconnect of CMOS Gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 13(12), Dec. 1994, pp. 1526--1535.

....at the output of a CMOS gate. Using this model we are able to compute the gate delay efficiently, within 25 of SPICE computed delays. Our parameters depend only on total interconnect tree resistance and capacitance at the output of the gate. Previous effective load capacitance methods [7, 9], applicable only for distributed RC interconnects, are based on Pi model parameters obtained via a recursive admittance moment computation. Our model should be useful for iterative optimization of performance driven routing or for estimation of gate delay and rise times in high level synthesis. ....

....model for driving point admittance which can be used in an iterative regime to accurately predict gate delays. The simplest approximation of the driving point admittance of the load interconnect tree is the total capacitance of the tree (C tot ) which is a (pessimistic) first order approximation [7, 8]. 1 For submicron technologies and MCM interconnects, the total interconnect resistance is large and comparable to the driver output resistance; it cannot be neglected in the gate delay calculations. The actual delay is much smaller than that derived from the lumped capacitance model, because ....

[Article contains additional citation context not shown here]

J. Qian, S. Pullela, and L. Pillage, "Modeling the "Effective Capacitance" for the RC Interconnect of CMOS gates", IEEE Trans. on CAD, December 1994, pp. 1526-1535.

....area routing. In these contexts, accurate estimation of gate delay and rise time depends on having an accurate model for the driving point admittance of a load interconnect tree at the output of a gate. Various approaches have been proposed to address the resulting effective capacitance problem [7, 15, 12, 6, 13]. In this paper, we improve the iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. We use an accurate driver resistance computation to enable effective capacitance calculation when the interconnect load is driven by complex gates, i.e. ....

....of the effective capacitance function allows the effective capacitance to be characterized over the full range of parameter values. Pileggi and coauthors propose an effective capacitance calculation that approximates the output waveform for single stage gates by using a two piece output waveform [15, 12]. This approach calculates an effective capacitance by equating (i) the current at the gate output with driving point admittance as the load, and (ii) the current at the gate output with a single effective capacitor as the load. It is difficult to obtain a single effective capacitance that will ....

J. Qian, S. Pullela, and L. Pillage, "Modeling the "Effective Capacitance " for the RC Interconnect of CMOS gates", IEEE Trans. on CAD 13 (1994), pp. 1526-1535.

....entry is in the form: ft t ; CL ; t d ; t f ; tr )g. Such a model can be very accurate if one can afford the time and space to generate a detailed multi dimensional table for each gate. Alternatively, one can store the characterization data much more compactly in the form of k factor equations [13, 14], such as: t d = k1 k2 Delta CL) Delta t t k3 Delta C 3 L k4 Delta CL k5 (6) t f = k 0 1 k 0 2 Delta CL) Delta t t k 0 3 Delta C 2 L k 0 4 Delta CL k 0 5 (7) where k1 Delta Delta Delta5 and k 0 1 Delta Delta Delta5 are determined based on linear ....

...., C2 and R in addition to the input transition time, etc. for driver delay computation. Since a very large look up table or complex k factor equations and very extensive simulations are needed to account for all possible combinations of C1 , C2 and R in a model, the effective capacitance model [14] was proposed to allow drivers to be still pre characterized in terms of a single load capacitance, even when used to drive distributed RC interconnects. The effective capacitance model first computes a model to approximate the driving point admittance, and then compute iteratively an effective ....

[Article contains additional citation context not shown here]

J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance " for the RC interconnect of CMOS gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 1526--1535, Dec. 1994.

....capacitance. 2 2. 2 O Brien Savarino P Model With thinner interconnect geometries, the resistive component of the gate load is comparable to or larger than the gate output resistance, and the gate doesnot see all of the capacitanceloading since the metal resistance shields some capacitance [11]. For example, if we increase the interconnect resistance of the load and keep the gate output resistance constant then the total gate delay at the output will decreasesince the interconnect resistance will tend to shield some of the load capacitance. In this case, while the total gate delay ....

....on the input slew rate and a single load capacitance, which represents the effect of the load. There are two different approaches in the literature for computing such an effective capacitance: i) McCormick s Effective Capacitance Model [6] and (ii) Pillage et al. s Effective Capacitance Model [11, 13]. The aim of each approach is to approximate the load at gate output using a single effective capacitance. 2.4 Open Ended RC P Model In a pre routing timing analysis, exact routing topology is not available. The paper [2] approximates an estimated interconnect tree by 2 The lumped capacitance ....

J. Qian, S. Pullela, and L. Pillage, "Modeling the "Effective Capacitance" for the RC Interconnect of CMOS gates", IEEE Trans. on CAD, December 1994, pp. 1526-1535.

....(i) the method of tot tot C R tot L 2 C = 5 6 tot C 1 C = 1 6 tot C tot R 1 R = 12 25 1 tot L = 12 25 L tot tot C R tot L Tree RLC (a) b) Figure 4: An open ended RLC line model to capture an RLC interconnect tree, and the RLC P model. McCormick [6] and (ii) the method of Pillage et al. [11, 13]. Both of these approaches are iterative in nature and are computationally expensive in the context of delay calculation, static timing analysis, etc. for iterative layout or performance optimization. McCormick s Effective Capacitance Model. In McCormick s approach, the effective capacitance is ....

....inverter response is slow, the gate will end up charging all the load capacitance. The range between C step and C tot is enforced by computing the Elmore delay of the gate load and the slew rate of the cell under a no load condition. Pillage et al. s Effective Capacitance Model. Pillage et al. [11, 13] calculate an effective capacitance by equating (i) the current at the gate output with driving point admittance as the load, and (ii) the current at the gate output with a single effective capacitor as the load. It is difficult to obtain a single effective capacitance that will exactly match the ....

[Article contains additional citation context not shown here]

J. Qian, S. Pullela and L. Pillage, "Modeling the "Effective Capacitance " for the RC Interconnect of CMOS gates", IEEE Trans. on CAD, December 1994, pp. 1526-1535.

....we can have a look up table for the fall time ratio of the driver. Another commonly used driver delay model pre characterizes the driver delay of each type of gate buffer in terms of the input transition time t t , and the total load capacitance C L in the following form of k factor equations [WeEs93, QiPP94]: t d f = k 1 k 2 Delta C L ) Delta t t k 3 Delta C 3 L k 4 Delta C L k 5 ; 18) t f = k 0 1 k 0 2 Delta C L ) Delta t t k 0 3 Delta C 2 L k 0 4 Delta C L k 0 5 ; 19) where k 1 Delta Delta Delta5 and k 0 1 Delta Delta Delta5 are determined based on ....

....of the interconnect and the sinks (Figure 4(a) and (b) However, not all the capacitance of the routing tree and the sinks are seen by the driver due to the shielding effect of the interconnect resistance, especially for fast logic gates with lower driver resistance. Qian, Pullela, and Pileggi [QiPP94] proposed the effective capacitance model which first uses a p model [OBSa89] to be discussed next (Figure 4(c) to better approximate the driving point admittance at the root of the interconnect (or equivalently, the output of the driver) and then compute iteratively the effective capacitance ....

[Article contains additional citation context not shown here]

J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "Effective Capacitance" for the RC Interconnect of CMOS Gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 13(12), Dec. 1994, pp. 1526-- 1535.

No context found.

J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance " for the RC interconnect of CMOS gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 1526--1535, Dec. 1994.

No context found.

J. Qian, S. Pullela, and L. T. Pileggi. Modeling the "effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 13(12):1526--1535, December 1994.

No context found.

J. Qian, S. Pullela, and L. T. Pileggi. Modeling the "effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 13(12):1526--1535, December 1994.

No context found.

J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance" for the RC interconnect of CMOS gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 1526--1535, Dec. 1994.

No context found.

J. Qian, S. Pullela, and L. Pillage. Modeling the "Effective Capacitance" for the RC Interconnect of CMOS Gates. IEEE Trans. on Computer-Aided Design, 13(12):1526--1535, December 1994.

No context found.

J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance" for the RC interconnect of CMOS gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 1526--1535, Dec. 1994.

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