J. K. Ousterhout, "Switch-level delay models for digital MOS VLSI," in Proc. Design Automation Conf, pp. 542--548, 1984. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
An Efficient Technique for Device and Interconnect Optimization.. - Cong, He (1997) (3 citations) (Correct)
....different sizes (100x and 400x) Different combinations of input transition times and output loads are used for measuring. As one can see, r 0 is clearly a function of size, input transition time and output load. Its value may differ by a factor of 2 (note that a similar observation was made in [22] as well, with smaller variation of effective resistance in the technology generation then) Furthermore, c 0 and c f are no longer sufficient to model a wire capacitance, due to increasing importance of coupling capacitance in DSM designs. We generated area capacitance (c a ) fringe capacitance ....
J. K. Ousterhout, "Switch-level delay models for digital MOS VLSI," in Proc. Design Automation Conf, pp. 542--548, 1984.
Systolic Combining Switch Designs - Dickey (1994) (Correct)
....than twice as fast as our non combining switch However, we have used a timing simulator to get process independent estimates of the critical path delay. The critical paths in a VLSI design are the slowest connections from an input on a clock phase to an output on that phase. We have used crystal [109], a timing analysis program developed at UC Berkeley and distributed as part of the Magic VLSI design tools, to find and optimize critical paths in our design. Table 4.4 shows delays for the worst paths in our design and for some other signals of interest as determined by crystal runs on ....
John K. Ousterhout. Switch-level delay models for digital MOS VLSI. Proceedings of the 21st Design Automation Conference, pages 542--548, June 1984.
A New Accurate and Hierarchical Timing Analysis Approach - Blaquière.. (Correct)
....accuracy. For others, the accuracy cannot be sacrificed and there is a need for efficient and accurate timing analysis. This need increases with the complexity and speed of VLSI systems. Speed up is usually achieved by sacrificing delay accuracy using abstract delay models, such as switch (e.g. [1, 2]) or block (e.g. 3] level instead of circuit level (e.g. 4] However, constraining timing analysis tools to less computationally expensive delay models and to a single abstraction level can result in unacceptable error margins. The computational effort required to achieve a given accuracy ....
....of the design generally results in a degradation of the computational time. The detailed results of this study will be presented elsewhere. 4 These values were pessimistically extracted from papers on the timing analyzers Crystal (switch level) and its modified ELogic version (circuit level) [2, 13]. iterate more than once with strategy P, in contrast to the other two strategies which always return TCP the first time. In strategy P, finding no critical instance is possible and, in this case, CP is re inserted in GPL if some paths of CG have not been enumerated. Moreover, the CP delay is ....
J. Ousterhout, "Switch-level delay models for digital MOS VLSI," in Proceedings of the ACM/IEEE Design Automation Conference, (Albuquerque, New Mexico), pp. 542--548, June 1984.
Modeling and Layout Optimization of VLSI Devices and Interconnects .. - Cong (Correct)
....driving point admittance for the net in (a) d) The same inverter driving the effective capacitance of the net in (a) The input signal has a transition time of t t . The slope model uses a one dimensional table to compute the effective driver resistance based on the concept of rise time ratio [26]. The effective resistance of a driver depends on the transition time of the input signal, the loading capacitance, and the size of the driver. In this model, the output load and transistor size are first combined into a single value called the intrinsic rise time of the driver, which is the ....
J. K. Ousterhout, "Switch-Level Delay Models for Digital MOS VLSI," Proc. 21st Design Automation Conf., 1984, pp. 542--548.
Interconnect Design for Deep Submicron ICs - Cong, Pan, He, Koh, Khoo (1997) (26 citations) (Correct)
....load C and matching the 50 delay of the driver driving the load with that of the equivalent RC circuit (0:7R eff C) under the step input. A more accurate model, called the slope model, uses a one dimensional table to compute the effective driver resistance based on the concept of rise time ratio [12]. It first uses the output load and transistor size to compute the intrinsic rise time of the driver, which is the rise time at the output under the step input. The input rise time of the driver is then divided by the intrinsic rise time of the driver to produce the rise time ratio of the driver. ....
J. K. Ousterhout, "Switch-level delay models for digital MOS VLSI," in Proc. Design Automation Conf, pp. 542--548, 1984.
Performance Optimization of VLSI Interconnect Layout - Cong, He, Koh, Madden (1996) (27 citations) (Correct)
....specifically, the input rise time in this case) and V n th is the threshold voltage of ntransistor. In the slope model (first proposed by Pilling and Skalnik [PiSk72] a one dimensional table for the effective driver resistance based on the concept of rise time ratio is proposed by Ousterhout [Ou84]. The effective resistance of a driver depends on the transition time of the input signal, the loading capacitance, and the size of the driver. In the slope model, the output load and transistor size are first combined into a single value called the intrinsic rise time of the driver, which is the ....
J. K. Ousterhout, "Switch-Level Delay Models for Digital MOS VLSI," Proc. 21st Design Automation Conf., 1984, pp. 542--548.
Interconnect Design for Deep Submicron ICs - Jason Cong Lei (Correct)
No context found.
J. K. Ousterhout, "Switch-level delay models for digital MOS VLSI," in Proc. Design Automation Conf, pp. 542--548, 1984.
Modeling and Optimization of VLSI Interconnects - He (1999) (Correct)
No context found.
J. K. Ousterhout. Switch-level delay models for digital MOS VLSI. In Proc. Design Automation Conf, pages 542--548, 1984. 199
Modeling and Optimization of VLSI Interconnects - He (1999) (Correct)
No context found.
J. K. Ousterhout. Switch-level delay models for digital MOS VLSI. In Proc. Design Automation Conf, pages 542--548, 1984. 163
Determination of Worst-Case Crosstalk Noise for Non-Switching.. - Chen, He (2002) (Correct)
No context found.
J. K. Ousterhout, "Switch-level delay models for digital MOS VLSI," in Proc. Design Automation Conf, pp. 542--548, 1984.
Determination of Worst-Case Crosstalk Noise for Non-Switching.. - Chen, He (2003) (Correct)
No context found.
J. K. Ousterhout, "Switch-level delay models for digital MOS VLSI," in Proc. Design Automation Conf, pp. 542--548, 1984.
Simultaneous Buffer and Wire Sizing for Performance and.. - Cong, Koh, Leung (1996) (1 citation) (Correct)
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J. K. Ousterhout, "Switch-Level Delay Models for digital MOS VLSI," in Proc. ACM/IEEE Design Automation Conf., 1984, pp. 542--548.
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