S.C. Ma, P. Franco, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experimental Results," Proc. Int'l Test Conf., pp. 663-672, 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....line and the V line, etc. Fault models deme the properties of the tests that will detect the faulty behavior caused by de fects. For example, stuck at 1 tests for line a will detect the defect caused by a bridge between the sig nal line a and V . dd It has been reported in the literature [5] that tests that detect every stuck at fault multiple times are better at dosing DPM holes than are tests that detect each fault only once. This approach, called N detection, works because each fault is generally targeted in several different ways, increasing the probability that the conditions ....

S.C. Ma, P. Franco, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results," Proceedings 1995.

....them to test sets for the earlier, less strict definition. The results show a simple criterion to decide when it may be necessary to combine the two definitions in order to obtain a high quality test set. 1. Introduction n detection test sets were shown to achieve improved defect coverage in [1] [6] An n detection test set is one where each modeled fault is detected either by n different tests, or by the maximum number of different tests that can detect the fault if this number is smaller than n. n detection test sets for stuck at faults in combinational circuits were considered in ....

....[1] 6] An n detection test set is one where each modeled fault is detected either by n different tests, or by the maximum number of different tests that can detect the fault if this number is smaller than n. n detection test sets for stuck at faults in combinational circuits were considered in [1] [4] Stuck at faults in sequential circuits were considered in [5] and transition faults in combinational and full scan circuits were considered in [6] In the experiments described in [1] and [3] chips were fabricated for the purpose of comparing various test sets and test application ....

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S. C. Ma, P. Franco and E. J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results", in Proc.

....detected [9] 10] 11] This paper shows some cases in which decreasing the power supply voltage could cause a fault which is detected at a higher power supply voltage to be undetected at a lower power supply voltage. Although this behavior has been predicted in [12] and experimentally observed in [13], it has not been proven by specific examples. This work demonstrates such cases with examples and discusses their impact on overall fault coverage. The remainder of this paper is organized as follows: Section 2 deals with the limitations of previous fault models, explains the fault model used in ....

....X in the table means that the fault is undetectable) The results of this simulation indicate that at decreased V DD , the bridging fault is undetectable for some test vectors, even though it is detectable at a higher value of V DD . Some test vectors can detect a higher bridging resistance. In [13], it was shown that some circuits escaped fault detection at low voltage even though the faults were detected at higher V DD . However, since bridging faults that fall under this case occur relatively few times in the ISCAS85 circuits, the impact of this behavior on overall fault coverage is ....

Siyad C. Ma, Piero Franco and Edward J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results," in Proc. Int. Test Conf., 1995, pp. 663672.

....1 1200W X 0 1 1 1 1200W X 1 1 0 1 1000W X 1 1 1 0 1000W X The results indicate that at decreased V DD , the bridging fault is undetectable for some vectors, even though it is detectable at higher V DD . But at low V DD some vectors can detect a higher bridging resistance. The measured data in [31] illustrate this behavior. This anomalous behavior at different values of V DD can have varying impacts on overall fault coverage. If the circuit under test has several case 4 faults, and these faults exhibit the behavior described, then the overall fault coverage may drop at decreased V DD . If ....

S. C. Ma, P. Franco, and E. J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results," Proc. Int. Test Conf., 1995, pp. 663-672.

....single stuck at faults are widely used for testing, it is now recognized that they are not always effective for non modeled faults and various defect types. In particular, since every modeled fault is now detected by fewer patterns, this approach can lead to reduced coverage of non modeled faults [9, 10, 11]. It was shown in [10] that detection test sets, in which every fault is detected by at least patterns ( and the average number of tests per fault is high, are more effective for detecting non modeled faults. Since uncompacted tests are applied to the SOC after on chip decompression, ....

.... compliant, it can be used for carrying out various other tests. 3 Enhanced defect coverage It has recently been shown that detection test sets, in which every fault is detected by ( tests, are more effective in detecting defects that are not modeled by stuck at faults [9, 10, 11]. In this section, we show that the uncompacted test sets that are applied to the core under test after decompression provide a higher degree of detection than ATPG compacted test sets. This in itself is not surprising since a large number of patterns are now being applied to the core under ....

S. C. Ma, P. Franco and E. J. McCluskey, "An experimental chip to evaluate test techniques experimental results", Proc. Int. Test Conf., pp. 663-672, 1995.

....More importantly, Pierzynska and Pilarski have shown that a non robust test can detect a delay fault undetectable by any robust test [19] Franco and McCluskey [20] and others [21] 22] 23] have proposed extensions to delay fault testing that address some of these difficulties. Recently, Ma, et al. [24] and others [3] 4] 25] 26] evaluated a large number of test methodologies and determined that a combination of several test strategies may be necessary in order to find all defective devices. In particular, Ma, et al. discovered that I DDQ cannot detect all kinds of defects and must be used with ....

S. C. Ma, P. Franco, and E. J. McCluskey. An experimental chip to evaluate test techniques: Experiment results. In International Test Conference, pages 663--672, 1995.

....chip is used in an experiment to evaluate the effectiveness of different test techniques. This report is part of a series that reported the results from the experiment. The chip and experiment design was described in ITC95[1,2] The preliminary results from wafer probe were also presented in ITC95[3]. The results for different clock rate and clocking mode in wafer probe were presented in ITC96[4] In VTS98[5] PRELIMINARY VERSION Copyright 1999 by the Center for Reliable Computing, Stanford University. All rights reserved, including the right to reproduce this report, or portions ....

Ma, S.C., et al., "An Experimental Chip to Evaluate Test Techniques Experiment Results," Proc. 1995 Intl. Test Conf., Washington, D.C., pp663-672, Oct. 21-25, 1995.

....[23] Lastly, Pierzynska and Pilarski have shown that a non robust test can detect a delay fault undetectable by any robust test [22] Franco and McCluskey [24] and others [25] 26] 27] have proposed extensions to delay fault testing that address some of these difficulties. Recently, Ma, et al. [28] and others [7] 8] 29] 30] evaluated a large number of test methodologies and determined that a combination of several test strategies may be necessary in order to find all defective devices. In particular, Ma, et al. discovered that I DDQ cannot detect all kinds of defects and must be used with ....

S. C. Ma, P. Franco, and E. J. McCluskey. An experimental chip to evaluate test techniques: Experiment results. In International Test Conference, pages 663--672, 1995.

....to quantify the non target defect detection of a given test pattern set. Although stuck at fault detection is widely accepted in industry as a key test quality figure of merit, it does not account for the necessity of detecting other defect types seen in real manufacturing environments [BUTL90][MA95]. Other researchers have addressed This work was supported by the Texas Advanced Technology Program Project No. 036327 152. this problem by using various enhanced fault models during the ATPG process [FERG91] In this case, the fault simulation engine is modified to allow the simulation of ....

Ma, S., France, P., and McCluskey, E.J., "An Experimental Chip to Evaluate Test Techniques: Experimental Results," Proc. International Test Conference 1995, pp. 663-672.

....fault n times, by n different tests. If a fault has m n different tests, a complete n detection test set should contain all m tests for the fault. The importance of n detection test sets is that they allow the stuck at fault model to be used in generating tests with high defect coverages [12]. Information about the number of detectable faults in the circuit SQR for n between 1 and 10 is shown in Table 4, as follows. Each row corresponds to a different value of n. Following n we show the number of faults that have at least n different tests. For example, from the entry for n = 5, 1628 ....

S. C. Ma, P. Franco and E. J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results", in Proc. 1995 Intl. Test Conf., Oct. 1995, pp. 663-672.

.... surrogates) are detected increases significantly [Pomeranz 98] In the Murphy test chip experiment, all the 116 defective chips were detected by single stuck at test sets that detect each single stuck at fault 3 or more times; however, the best 100 stuck at test set missed 2 defective chips [Ma 95] It was later observed that all N detect test sets have higher transition fault coverage than other 100 SSF test sets. In [Grimaila 99] it was reported that the defect level was improved by 1288dpm, after applying N detect single stuck at test sets. Therefore, N detect single stuck at fault ....

Ma, S.C., P. Franco, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques: Experimental Results," Proc. 1995 International Test Conference, pp. 663-672, 1995.

....was to get a real world comparison of many different test methods, as it is difficult to evaluate the effectiveness of tests without experimental data. The design of the experiment and architecture of the Test Chip were described in [1] and preliminary experimental results were presented in [2]. This paper presents results for different clock speeds and clocking modes (at speed and delay) and uses this data together with the data from the on chip failure counters to characterize the behavior of the defective parts. Almost 44 of the defective parts were found to be timing or pattern ....

....test set. Most of these test sets were applied at both a normal supply voltage (V DD =5V) and at very low supply voltage (V DD =1.7V) This paper will focus on tests at normal supply voltage. Results for CrossCheck and a preliminary analysis of Very Low Voltage and IDDQ tests were reported in [2]. Apart from IDDQ and CrossCheck tests, output responses of all test sets were captured by both sampling the output voltage and Stability Checking. 3.2 Test Conditions Each test set was applied to the Test Chip under different test conditions to evaluate the different testing techniques used in ....

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Ma, S.C., P. Franco, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques, Experiment Results," Proc. 1995 Int. Test Conf., Washington, DC, Oct. 23-25, 1995.

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S.C. Ma, P. Franco, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experimental Results," Proc. Int'l Test Conf., pp. 663-672, 1995.

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S. Ma, P. Franco, and E. McCluskey, "An experimen-tal chip to evaluate test techniques experimental results," in Proceedings IEEE International Test Conference (ITC), pp. 663--672, Apr. 1995.

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