A. B. Kahng and C.-W. A. Tsao, "Low-Cost Single-Layer Clock Trees with Exact Zero Elmore Delay Skew," Proc. IEEE Int'l Conf. on Computer-Aided Design, 1994, pp. 213--218.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....clock routing problem was first studied by Zhu and Dai [20] They proposed the Max Min algorithm which assumes a given source location. The two key components of the Max Min algorithm are governed by the Max rule and the Min rule, respectively. The Planar DME algorithm proposed by Kahng and Tsao [12] is that a single top down pass can produce the same output as the two path DME algorithm at the expense of computation time under the path length delay model. The Max Min and Planar DME algorithms achieve planarity through higher routing costs measured by the total wire length. As mentioned, ....

A. Kahng and C. Tsao, "Low-cost single-layer clock trees with exact zero Elmore delay skew," Proceedings IEEE International Conference on Computer-Aided Design, pp. 213-218, 1994. Page 20

....uses a recursive bottom up strategy, building up a zero skew tree (ZST) by recursively merging zero skew subtrees. Figure 4 shows a zero skew tree construction. The original ZST algorithm has undergone improvements to minimize wire length [47] and to guarantee planarity of the resulting tree [27]. Wire sizing When choosing the wire width of the route for a net, a careful tradeoff has to be made. If minimum design rules are used for a long wire, the wire resistance will cause large delays. On the other hand, the wire cannot be made arbitrarily wide, since its capacitance will then ....

A. B. Kahng and C. W. A. Tsao. " Low-Cost Single Layer Clock Trees With Exact Zero Elmore Delay Skew ". In ICCAD, pages 213--218, November 1994.

....clock topology [2] or combined with a clock topology generation algorithm to achieve zero skew with smaller wirelength [7] Currently, researches on clock routing are moving along a few directions. Zero skew planar routing was first proposed by [18] using Max Min operations and followed up by [12, 13] using single phase DME algorithm. Other work includes buffer insertion [9, 3] process variation tolerant skew minimization [15, 4, 14] and a clock router that accomplished specified pin to pin delay [16] The emphasis of most of the current clock routing algorithms is on achieving zero skew at ....

A. B. Kahng and C.-W. A. Tsao, "Low-cost single-layer clock trees with exact zero Elmore delay skew," Proc. IEEE Int'l Conf. on Computer-Aided Design, 1994, pp. 213--218.

....sinks (a) source topological routing (b) source geometrical embedding (c) Figure 3.1: a) source and five sinks in R 2 . b) planar equal path length clock tree. c) geometrical embedding resulting in a rectilinear clock tree. more recent research on the planar clock routing has been done [KT94] which modifies the deferred merge embedding (DME) method to construct a planar equal path length clock tree. 3.2 Problem Formulation and Overview Planar Equal Path Length Clock (Steiner) Tree Problem: Given a source point s and a set of sinks, find a planar clock (Steiner) tree T , with the ....

A. Kahng and C.-W. A. Tsao. Low-cost single-layer clock trees with exact zero elmore delay skew. In Digest of Tech. Papers of IEEE Intl. Conf. on Computer Aided Design, pages 213--218, 1994. References 121

....to a given clock topology [2] or combined with a clock topology generation algorithm to achieve zero skew with smaller wirelength [7] Currently, research on clock routing is moving along a few directions. Zero skew planar routing was first proposed by [18] using Max Min operations, followed up by [12, 13] using single phase DME algorithm. Other work includes buffer insertion [9, 3] process variation tolerant skew minimization [15, 4, 14] and a clock router that accomplished specified pin to pin delay [16] The emphasis of most of the current clock routing algorithms is on achieving zero skew at ....

A. B. Kahng and C.-W. A. Tsao, "Low-cost single-layer clock trees with exact zero Elmore delay skew," Proc. IEEE Int'l Conf. on Computer-Aided Design, 1994, pp. 213--218.

....algorithm for zero skew tree to BST DME algorithms by the enabling concept of a merging region, which generalizes the merging segment concept of [BoKa92, ChHH92a, Ed91] for zero skew clock trees. Recent studies on clock routing have also led to new methods for single layer (planar) clock routing [ZhDa92, KaTs94a, KaTs94b]. Furthermore, a number of authors have applied wiresizing optimizations and or buffer optimizations to minimize phase delay [PuMO93, Ed93b, MePP93, PuMP93] skew sensitivity to process variation [PuMO93, ChCh94, LiWo94, XiDa95] and or power dissipation [PuMO93, ViMa95] Most of these works are ....

....routing tree and the Min rule aims to reduce the routing cost. The two rules guarantee that the tree produces by the algorithm is planar and has zero pathlength skew and the pathlength delay is minimal. 5.3. 2 Planar DME Clock Routing The key to the Planar DME algorithm proposed by Kahng and Tsao [KaTs94a, KaTs94b] is that a single top down pass can produce the same output as the two phase DME algorithm at the expense of computation time under the pathlength delay model. This stems from the following facts [BoKa92] i) Given a set of sinks S with diameter diameter(S) if one constructs for each sink s i in ....

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A. B. Kahng and C.-W. A. Tsao, "Low-Cost Single-Layer Clock Trees with Exact Zero Elmore Delay Skew," Proc. IEEE Int'l Conf. on Computer-Aided Design, 1994, pp. 213--218.

No context found.

A. B. Kahng and C.-W. A. Tsao, "Low-Cost Single-Layer Clock Trees with Exact Zero Elmore Delay Skew," Proc. IEEE Int'l Conf. on Computer-Aided Design, 1994, pp. 213--218.

....As described, Planar DME uses very simple embedding and partitioning rules to guarantee planarity. Better partitioning strategies are possible, e.g. the splitting line can be changed to a splitting path of two or more line segments. Preliminary trials of such an approach are very promising [13]; improving the embedding rules seems harder and less promising than improving the partitioning rules. A second major extension of Planar DME involves a b c d e h f g P P P 0 s a b c Figure 5: Example with 9 sinks (squares at leaf nodes in tree) illustrating the execution of Planar DME. The ....

....algorithms for the linear delay model, using MCNC benchmarks Primary1 (P1) and Primary2 (P2) and benchmarks r1 through r5 from Tsay [14] The clock source locations are not given. Average cost savings over [15] are 15:5 . its applicability to more sophisticated delay models such as Elmore delay [13]. Our intuition is that topdown partitioning is more global than bottom up methods: a top down strategy can easily enforce planarity of the resulting solution, and is the logical candidate for extension into more sophisticated clock tree constructions. Finally, a more practical clock tree ....

A. B. Kahng and C.-W. Albert Tsao. "Low-Cost SingleLayer Clock Trees With Exact Zero Elmore Delay Skew," Proc. IEEE Intl. Conf. on Computer-Aided Design (to appear) , 1994.

....Figure will shrink to be within the shortest distance region SDR(y; z) Thus, like the merging regions constructed by the BME method, the planar merging regions will contain all the minimumcost merging points when no detouring occurs. For the same reason stated in the Elmore PlanarDME algorithm [18] the planar merging regions along the shortest planar path will not guarantee minimum tree cost at the next higher level. Thus, it is possible to construct and maintain planar merging regions along several shortest planar paths. At the same time, if an internal node v can have multiple planar ....

....have identical 0:5pF loading capacitance and the per unit wire resistance and wire capacitance are 16:6m Omega and 0:027fF . For each internal node, we maintain at most k = 5 merging regions with lowest tree cost. We use the procedure Find Shortest Planar Path of the ElmorePlanar DME algorithm [18] to find shortest planar s t paths. The current implementation uses Dijkstra s algorithm in the visibility graph G(V; E) e.g. 2] 24] where V consists of the source and destination points s, t along with detour points around the corners of obstacles. The weight jej of edge e = p; q) 2 E ....

[Article contains additional citation context not shown here]

A. B. Kahng and C.-W. Albert Tsao. Low-cost singlelayer clock trees with exact zero elmore delay skew. In Proc. IEEE Intl. Conf. Computer-Aided Design, 1994.

....merging points inside merging regions. 1 Introduction Control of signal delay is important in layout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model [17, 5, 11] and given new single layer (planar) constructions [18, 15, 16]. A detailed review of clock tree and Steiner routing algorithms is given in [14] In practice, circuits will operate correctly within a given skew tolerance, and indeed exact zero skew is never an actual design requirement [14] Two recent works [8, 12] have addressed the bounded skew routing ....

A. B. Kahng and C.-W. A. Tsao, "Low-Cost Single-Layer Clock Trees with Exact Zero Elmore Delay Skew," Proc. IEEE Int'l Conf. on Computer-Aided Design, 1994, pp. 213--218.

No context found.

A. B. Kahng and C.-W. A. Tsao, "Low-cost single-layer clock trees with exact zero Elmore delay skew," Proc. IEEE Int'l Conf. on Computer-Aided Design, 1994, pp. 213--218.

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