A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved planar zeroskew clock routing with minimum pathlength delay," in Proc. European Design Automation Conf., 1994, pp. 440--445.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....by radius minimization, with direct paths between the driver and all sink nodes. Shortest path trees rooted at the source achieve this goal. A number of works address the radius objectives, both for general path length minimization, and also for skew minimization in clock nets [3] 6] 13] [20]. A minimum radius construction with a suitable root point may be also be a minimum diameter construction. When there are multiple sources and sinks, path length minimization can be achieved by minimizing the maximum distance between any pair of nodes, which leads to diameter o minimization. p ....

....rectangle. connecting the center of the circle to each point in the set was shown to have the minimum diameter possible of any Steiner tree over the points. We follow their general approach, but address the Manhattan plane and also pursue tree length minimization. The work in [3] 6] 13] and [20] can be used to construct minimum diameter trees, but they are concerned mainly with skew minimization instead of total tree length minimization. The Manhattan minimum diameter Steiner tree problem has not been explicitly studied in the literature. Our work studies the construction of minimum ....

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A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved planar zeroskew clock routing with minimum pathlength delay," in Proc. European Design Automation Conf., 1994, pp. 440--445.

....clock topology [2] or combined with a clock topology generation algorithm to achieve zero skew with smaller wirelength [7] Currently, researches on clock routing are moving along a few directions. Zero skew planar routing was first proposed by [18] using Max Min operations and followed up by [12, 13] using single phase DME algorithm. Other work includes buffer insertion [9, 3] process variation tolerant skew minimization [15, 4, 14] and a clock router that accomplished specified pin to pin delay [16] The emphasis of most of the current clock routing algorithms is on achieving zero skew at ....

A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved planar zero-skew clock routing with minimum pathlength delay," Proc. EuropeanDesign Automation Conference, 1994.

....can be obtained by radius minimization, with direct paths between the driver and all sink nodes. Shortest path trees rooted at the source achieve this goal. A number of works address the radius objectives, both for general path length minimization, and also for skew minimization in clock nets[13, 3, 6, 20]. A minimum radius construction with a suitable root point may be also be a minimum diameter construction. When there are multiple sources and sinks, path length minimization can be achieved by minimizing the maximum distance between any pair of nodes, which leads to diameter minimization. Our ....

....diameter circle, a star topology connecting the center of the circle to each point in the set was shown to have the minimum diameter possible of any Steiner tree over the points. We follow their general approach, but address the Manhattan plane and also pursue tree length minimization. The work in [13, 3, 6, 20] can be used to construct minimum diameter trees, but they are concerned mainly with skew minimization instead of total tree length minimization. The Manhattan minimum diameter Steiner tree problem has not been explicitly studied in the literature. Our work studies the construction of minimum ....

[Article contains additional citation context not shown here]

A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved Planar Zero-Skew Clock Routing with Minimum Pathlength Delay," Proc. European Design Automation Conf., pp. 440-445, 1994.

....to a given clock topology [2] or combined with a clock topology generation algorithm to achieve zero skew with smaller wirelength [7] Currently, research on clock routing is moving along a few directions. Zero skew planar routing was first proposed by [18] using Max Min operations, followed up by [12, 13] using single phase DME algorithm. Other work includes buffer insertion [9, 3] process variation tolerant skew minimization [15, 4, 14] and a clock router that accomplished specified pin to pin delay [16] The emphasis of most of the current clock routing algorithms is on achieving zero skew at ....

A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved planar zero-skew clock routing with minimum pathlength delay," Proc. European Design Automation Conference, 1994.

....algorithm for zero skew tree to BST DME algorithms by the enabling concept of a merging region, which generalizes the merging segment concept of [BoKa92, ChHH92a, Ed91] for zero skew clock trees. Recent studies on clock routing have also led to new methods for single layer (planar) clock routing [ZhDa92, KaTs94a, KaTs94b]. Furthermore, a number of authors have applied wiresizing optimizations and or buffer optimizations to minimize phase delay [PuMO93, Ed93b, MePP93, PuMP93] skew sensitivity to process variation [PuMO93, ChCh94, LiWo94, XiDa95] and or power dissipation [PuMO93, ViMa95] Most of these works are ....

....case of four sinks at the corners of a unit square, an X tree connection can be embeddedon a rectilinear plane using a cost of 4 units, whereas an H tree connection requires only a cost of 3 units. An X tree is more costly due to overlapping routing when it is realized on a rectilinear plane [KaTs94a]. The set of sinks are then ordered by their x and y coordinates. If S is to be partitioned in the x (y) direction, then sinks in the first half of the ordered sink set are grouped in the S le f t (S bottom ) partition and the rest of the sinks belong to the S right (S top ) partition. The ....

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A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved Planar Zero-Skew Clock Routing with Minimum Pathlength Delay," Proc. European Design Automation Conf., 1994, pp. 440-445.

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A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved Planar Zero-Skew Clock Routing with Minimum Pathlength Delay," Proc. European Design Automation Conference, 1994, pp. 440-445.

....zero skew subtree over any sink set S 0 , notably that the root of the subtree over S 0 must be located at center(S 0 ) The following Facts and Theorem are crucial to the development of the Single Pass DME and then PlanarDME algorithms. Proofs for the three Facts can be found in [12]. Fact 1: For any sink set S and topology G, let S v be the set of sinks in the subtree rooted at v in the DME solution. Let t LD (u) be the linear delay (i.e. pathlength) from point u 2 ms(v) to each sink in S v . Then t LD (u) radius(S v ) Fact 2: Let G be the connection topology of the ....

....polygon, so long as neither S 0 1 or S 0 2 is empty. In the example of Fig. 2, S 0 = fa; bg is divided into S 0 1 = fag and S 0 2 = fbg, and P S 0 is divided into P S 0 1 and P S 0 2 accordingly. A total of Theta(jS 0 j) time is needed to partition the sinks in set S 0 . [12] shows that these embedding and partitioning rules satisfy the following: Theorem 2: Given a subset S 0 S, a convex polygon PS 0 containing S 0 , and a point p inside PS 0 , i) the embedding rules will select a feasible embedding point v inside P S 0 (thus the routing from p to v ....

A. B. Kahng and C.-W. Albert Tsao. "Planar-DME: Improved Planar Zero-Skew Clock Routing With Minimum Pathlength Delay," technical report UCLA CSD-940006, February 1994.

....With Exact Zero Elmore Delay Skew Andrew B. Kahng and Chung Wen Albert Tsao UCLA Computer Science Dept. Los Angeles, CA 90024 1596 USA Abstract We give the first single layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear Planar DME method [11] guarantees a planar solution under the linear delay model. In this paper, we use a Linear Planar DME variant connection topology to construct a low cost zero skew tree (ZST) according to the Elmore delay model. While a linear delay ZST is trivially converted to an Elmore delay ZST by detouring ....

....for this work was provided by NSF MIP9223740 and MIP 9257982. We thank Kenneth Boese and Masato Edahiro for use of their DME codes. top down partitioning approach of [10] with the ZhuDai construction. Both [16, 13] rely on the linear delay model to achieve their results. 1. 1 Single Pass DME In [11], we showed that under linear delay the twophase DME algorithm can be emulated by a topdown Single Pass DME . More precisely, the tree of merging segments constructed in the bottom up DME phase can be generated during the top down phase. 1 The enabling result is that the root of the ....

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A. B. Kahng and C.-W. A. Tsao. "Planar-DME: Improved Planar Zero-Skew Clock Routing With Minimum Pathlength Delay," Proc. ACM/IEEE European Design Automation Conf., September 1994.

.... for the zero skew case [6, 7] and for the infinite skew case (i.e. the Steiner minimal tree problem) 2, 13] 3) For arbitrary topology and single layer (planar) embedding, the Extended Planar DME (ExP DME) algorithm exactly matches the best known heuristic for zero skew planar routing [15], and again closely approaches the best known performance for the infinite skew case. Our work provides unifications of the clock routing and Steiner tree heuristic literatures, and gives a smooth cost skew tradeoff that allows good engineering solutions. 1 Introduction In routing design for ....

....2, we review the DME (Deferred Merge Embedding) approach to zero skew clock tree construction; the DME approach is central to our proposed methodology. Specifically, we summarize the original DME method, the Greedy DME method of Edahiro [6] and the Planar DME method of Kahng and Tsao [15]. In Section 3, we develop our first tradeoff heuristic, for the minimum cost BST with fixed topology. This construction is optimal for the extreme cases of B = 0 and B = 1 (i.e. the SMT problem with fixed topology) Section 4 develops our second heuristic, for the case of unrestricted topology ....

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A. B. Kahng and C.-W. A. Tsao. "Planar-DME: Improved Planar Zero-Skew Clock Routing With Minimum Pathlength Delay," Proc. ACM/IEEE European Design Automation Conf., September 1994.

....with non convex polygons becoming further divided into smaller convex polygons within the succeeding two or three levels. Furthermore, such variants can achieve averages of up to 10.9 wirelength reduction versus results for the original Linear Planar DME algorithm which we have reported in [17]. We now briefly describe two possible Linear Planar DME variants. Using a Splitting Path Consider a subset of sinks S 0 S that is being partitioned, with jS 0 j 2. Recall that the splitting path consists of line segment pv and v, a ray emanating from v. The line segment pv has been ....

A. B. Kahng and C.-W. A. Tsao. "Planar-DME: Improved Planar Zero-Skew Clock Routing With Minimum Pathlength Delay," Proc. ACM/IEEE European Design Automation Conf., September 1994.

....(to be constructed in the second major step of our approach) over sinks in cluster X i . In other words, Cap(X i ) P v 2 X i c v d(l(v) center(X i ) Delta c, where c v is the input capacitance of node v and center(X i ) is the Manhattan center of the nodes in cluster X i as defined in [19], 20] 6 ffl The number w is used to trade off between balance among clusters and the total capacitive load of all clusters. A higher value of w favors balanced clustering, which usually leads to lower cost routing at the next higher level but can cause large total capacitive load at the ....

A. B. Kahng and C.-W. Albert Tsao. Planar-dme: Improved planar zero-skew clock routing with minimum pathlength delay. In Proc. European Design Automation Conf. with with EURO-VHDL, pages 440-- 445, Grenoble, France, September 1994. Also available as technical report CSD-940006, Computer Science Dept., UCLA.

....length of each edge of the clock tree (e.g. linear delay and Elmore delay) For linear delay, DME is optimal: it returns a tree with minimum cost and minimum source sink pathlength for any input sink set S and topology G. We now review DME and its Greedy DME and Planar DME variants, following [1, 14]. We identify each node v of the rooted topology G with the edge ev to its parent. Once a node v of the topology has been embedded in the Manhattan plane, we often identify v with its location in the plane, denoted l(v) The cost of a routing tree T is defined as cost(T ) P v2T jev j, i.e. ....

....between 2 and 4. The solution is improved by a post processing local search that adjusts the resulting topology (cf. CL I6 in [7] Greedy DME achieves 20 reduction in wiring cost compared with the methods of [3] The Planar DME Algorithm Finally, the Planar DME algorithm of Kahng and Tsao [14] determines node embeddings and connection topology by top down partitioning of the routing area and the sink set. Given S 0 S and a convex polygon P S 0 containing S 0 , Planar DME recursively divides P S 0 into two smaller convex polygons, such that routing inside one convex polygon ....

[Article contains additional citation context not shown here]

A. B. Kahng and C.-W. A. Tsao. "Planar-DME: Improved Planar Zero-Skew Clock Routing With Minimum Pathlength Delay," Proc. ACM/IEEE European Design Automation Conf., September 1994.

....merging points inside merging regions. 1 Introduction Control of signal delay is important in layout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model [17, 5, 11] and given new single layer (planar) constructions [18, 15, 16]. A detailed review of clock tree and Steiner routing algorithms is given in [14] In practice, circuits will operate correctly within a given skew tolerance, and indeed exact zero skew is never an actual design requirement [14] Two recent works [8, 12] have addressed the bounded skew routing ....

....become closer without much change in the subtree costs. As a result, this version of ExG DME also very closely matches one of the best known heuristics for unbounded skew routing [3] The work of [12] also gives an Extended Planar DMEmethod which again matches the best known heuristics [15] when the routing tree must be embeddable on a single layer. 3 The Boundary Merging and Embedding Method Wenow present our BoundaryMergingandEmbedding(BME) method, which encompassesthe straightforward generalizations of Ex DME and ExG DME from pathlength to Elmore delay. The difference from [8, ....

A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved Planar Zero-Skew Clock Routing with Minimum Pathlength Delay," Proc. European Design Automation Conference, 1994, pp. 440-445.

No context found.

A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved planar zeroskew clock routing with minimum pathlength delay," in Proc. European Design Automation Conf., 1994, pp. 440--445.

No context found.

A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved planar zero-skew clock routing with minimum pathlength delay," Proc. EuropeanDesign Automation Conference, 1994.

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