J. P. Fishburn, "Clock skew optimization," IEEE Transactions on Computers, vol. 39, pp. 945--951, July 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....network, solving a computationally inexpensive subproblem at each intermediate step. An additional feature of this work is that it can be extended very easily to build clock trees with prespecified nonzero skews for cases when deliberate skews are used in the clock network for cycle borrowing [6]. To blend the advantages of meshes and trees, we propose a hybrid mesh tree structure that is guaranteed to have zero skew under the Elmore delay metric, and further optimize this structure to a target transition time and small non zero skew under a higher order delay model. One example of our ....

J. P. Fishburn, "Clock skew optimization," IEEE Transactions on Computers, vol. 39, pp. 945-951, Jul. 1990.

....decreasing the size of the output driver to achieve less power. 3. CLOCK SKEW SCHEDULING APPLIED TO CRITICAL DATA PATHS The concept of slowing down fast data paths in order to save power can be further applied to slower, more critical data paths with the aid of non zero clock skew scheduling [4, 7]. Given two sequentially adjacent registers, the clock skew between these two registers is defined as HVU h X4 b H:Y H Y , where H Y H Y are the clock delays from the clock source to the registers, respectively. If the clock delay to the initial register H:Y is greater ....

....initial register H:Y is greater than the clock delay to the final register H:Ys , the clock skew is described as positive. Similarly, if the clock delay to the initial register is less than the clock delay to the final register , the clock skew is described as negative. As described in [4, 7, 8], the individual clock skew for each data path should satisfy the following two constraints: H YZ U h X s k H ZVa m (2) H Z. H U h X4 5 HV T P (3) PgS .5 PgS .A 4A A P 7.A 7g A Pg S45 S a5 4A P A P7 s5 7ggsA [ 5 Figure 3: Application ....

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J. P. Fishburn, "Clock Skew Optimization," IEEE Transactions on Computers, Vol. 39, No. 7, pp. 945-951, July 1990.

....signals are designed to arrive at with a delay , however, the permissible skew range is [ 2, 4] and delay tolerance increases to 6 tu. A retimed version of the original circuit that is obtained by shifting forward is shown in Fig. 2(b) In this case, the intersection of the two skew ranges is [ 1, 7]. When clock skew is zero, the permissible range of is [ 1, 1] and tolerance drops to 2 tu. When the arrival time of the clock signal at is delayed by , however, the permissible range becomes [ 1, 7] and tolerance increases to 8 tu. This value is the maximum tolerance that can be achieved by ....

....shifting forward is shown in Fig. 2(b) In this case, the intersection of the two skew ranges is [ 1, 7] When clock skew is zero, the permissible range of is [ 1, 1] and tolerance drops to 2 tu. When the arrival time of the clock signal at is delayed by , however, the permissible range becomes [ 1, 7], and tolerance increases to 8 tu. This value is the maximum tolerance that can be achieved by simultaneous retiming and clock scheduling for tu. An interesting observation about the retimed circuit in Fig. 2(b) is that when skews are zero, the delay tolerance of this circuit is smaller than that ....

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J. P. Fishburn, "Clock skew optimization," IEEE Trans. Computers, vol. 39, pp. 945--951, July 1990.

....by up to 20 over zero skew based systems. 1. INTRODUCTION Clock skew occurs when the clock signals arrive at sequentially adjacent storage elements at different times. Although it has been shown that intentional clock skew can be used to improve the clock frequency of a synchronous circuit [1, 2, 3, 4, 5, 6], clock skew is typically minimized when designing the clock distribution network, since unintentional clock skew due to process parameter variations may limit the maximum frequency of operation, as well as cause circuit failure independent of the clock frequency (i.e. race conditions) In [1,2] ....

.... 5, 6] clock skew is typically minimized when designing the clock distribution network, since unintentional clock skew due to process parameter variations may limit the maximum frequency of operation, as well as cause circuit failure independent of the clock frequency (i.e. race conditions) In [1,2], it is demonstrated that double clocking (the effect of the same clock pulse triggering the same data into two adjacent storage elements) can be prevented when the clock skew between these storage elements satisfies T Skewij T PDmin , where T PDmin is the minimum propagation delay of the path ....

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J. P. Fishburn, "Clock Skew Optimization," IEEE Transactions on Computers, Vol. C-39, No. 7, pp. 945-951, July 1990.

....clocking is an important way in which HLS differs from combinational logic implementation. The rephasing optimization in [1] provides a good example of how this can be used. Even in sequential logic synthesis, variable phase clocking has been considered in such forms as clock skew optimization [4] and shimming delays [5] To the best of our knowledge, there does not appear to be any other timing model that addresses this issue. Using conventional models, a complicated subsystem containing sequential elements will need to be represented in full in the context of the overall system design, ....

J. P. Fishburn, "Clock skew optimization," IEEE Transactions on Computers, vol. 39, pp. 945--951, Jul 1990.

....with fixed signal propagation delays between registers, there exists a lower bound of the clock period in semi synchronous framework which is usually smaller than the maximum signal delay between registers. This lower bound is achieved if the clock is distributed to each register at proper timing [11, 8, 19]. The clock timing of register is the difference in clock arrival time between the register and an arbitrary chosen (perhaps hypothetical) reference register. The set of clock timings is called a clock schedule. It is shown that an arbitrary clock schedule can be realized by constructing a clock ....

....time between v and an arbitrary chosen (perhaps hypothetical) reference register. The set of clock timings is called a clock schedule. We assume the framework that a circuit works correctly if the following two types of constraints are satisfied for every register pair with signal propagation [11]: No Double Clocking (Hold) Constraints : d min (u, v) No Zero Clocking (Setup) Constraints : T d max (u, v) where T is the clock period and d max (u, v) d min (u, v) is the maximum (minimum) propagation delay from register u to register v along a combinatorial circuit. These ....

J. P. Fishburn. Clock skew optimization. IEEE Trans. on Computers, 39(7):945--951, 1990.

.... registers in a hardware implementation, but are more flexible in that they do not impose the restriction that all the delay elements are activated at the same instant of time [2, 3, 4] This kind of variable phase clocking has been recognized as a useful feature even in sequential logic synthesis [5, 6]. In multirate systems under the SDF model, the most common interpretation of execution time is as follows: each vertex is assumed to be enabled when sufficient dataflow tokens have enqueued on its inputs. Once enabled, it can fire at any time, consuming a number of tokens from each input edge ....

J. P. Fishburn, "Clock skew optimization," IEEE Trans. on Computers, vol. 39, no. 7, pp. 945--951, Jul 1990.

....clocking is an important way in which HLS differs from combinational logic implementation. The rephasing optimization in [1] provides a good example of how this can be used. Even in sequential logic synthesis, variable phase clocking has been considered in such forms as clock skew optimization [4] and shimming delays [5] To the best of our knowledge, there does not appear to be any other timing model that addresses this issue. Using conventional models, a complicated subsystem containing sequential elements will need to be represented in full in the context of the overall system design, ....

J. P. Fishburn, "Clock skew optimization," IEEE Transactions on Computers, vol. 39, pp. 945--951, Jul 1990.

....trade circuit performance with circuit robustness. Techniques that offer a significant improvement in performance over zero skew clocking without affecting circuit yield have been developed and applied to RSFQ circuits [27, 30] Similar schemes have been proposed earlier for semiconductor logic [31, 32, 33], but these approaches have not as yet been widely accepted. The primary reasons are conservative design conventions used within industry, complex design procedures [32, 34, 35] relatively small performance improvements (up to 40 ) and difficulties in implementing well controlled delay lines ....

J.P. Fishburn, #Clock Skew Optimization,# IEEE Trans. Comput., vol. 39, 1990, pp. 945-951. 26

....value for each local data path. A consistent clock skew schedule is determined by application of the optimization algorithm described in this paper. This algorithm minimizes the least square error between the computed clock skew schedule and the objective clock skew schedule. As in previous work [1 5], a secondary objective of the clock skew scheduling algorithm is to increase the systemwide clock frequency. The paper begins with reviewing the circuit graph model in Sec. II. The formulation of the clock skew scheduling problem This research was supported in part by the National Science ....

....local data paths are characterized by a minimum and a maximum signal propagation delay from Q i to D f . The clock signals C i and C f are delivered to 1 2 and 143 with delays t 2 d and t 3 d , respectively, whereas the algebraic difference, t 2 d 5 t 3 d , is known as the clock skew [1, 4, 5]. Note that depending on the path direction and t 2 d and t 3 d , the clock skew as defined above may be negative, zero, or positive [5] 0 7803 5832 X 99 10.00 1999 IEEE. 6 # 687 # 6:9 ; BA . A ; ....

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J. P. Fishburn, "Clock Skew Optimization," IEEE Transactions on Computers, Vol. C--39, pp. 945--951, July 1990.

....(EP) between successive register banks [13] Chip measurements have been done using random numbers as well as sixteen vectors that toggle, in each clock cycle, at least 93 of the multiplier output bits. The last sequence makes easy to detect pipeline problems like doubleclocking and zero clocking [14] but also produces an increment of both datapath and off chip power consumption. Although each sub circuit has been tested at a complete set of frequencies, the following analysis have been particularized to 5 MHz for the FPGAs and 50 MHz for the SC circuit. 3.1 FPGA based circuits In Xilinx ....

J. Fishburn, "Clock Skew Optimization", IEEE Trans. on Computers, pp.945-951, July 1990.

....Computer Science, Minneapolis, MN 55455. 1 Introduction More accurate timing analysis tools are required in order to design faster digital systems. For example, minimizing clock period in a synchronous system is very critical for improving the circuit performance. In several previous approaches [9, 6, 2, 5, 10], it has been shown that the determination of an optimal clocking period highly depends on the accuracies of the estimated longest path length and shortest path length in a combinational circuit. F F b a L S OUT IN C B A PO PI Figure 1: A stage in a synchronous circuit Figure 1 shows a ....

....The simplest way to calculate the SR is to approximate L (S) as L S (S S ) where L S (S S ) is the length of the statically longest (shortest) path in circuit C. L S (S S ) can be computed easily once the circuit graph is created. Most previously published results on optimal clocking [9, 6, 5, 10] adopted this static approach. In the static approach, the functionality of a circuit is completely ignored, and the arrival time of a signal is calculated with the assumption that this signal propagates over all the paths which are statically connected to it. Clearly, SR (L E ;S E ) SR (L S ....

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J. P. Fishburn. Clock Skew Optimization. IEEE TC, 39(7):945--951, 1990.

....clock scheduling have usually been investigated separately. Retiming has been investigated for a variety of clocking disciplines [7, 9, 11, 16] delay models [8, 17] and optimization objectives [1, 4, 13, 15] A linear programming formulation of the clock scheduling problem was first described in [5]. A graph theoretical approach to clock scheduling was presented in [3] The combined application of retiming and clock scheduling was discussed in [12] Retiming and clock scheduling for maximum tolerance to delay variations under setup and hold constraints was investigated in [10] A two step ....

....0 ) Gamma s(e) This increase may remove a long path violation or introduce a short path violation. In the clock scheduling problem, the clock skews are adjusted so that no setup or hold violations exist in the circuit. A linear programming framework for clock scheduling was first presented in [5]. A graph theoretic approach to clock scheduling was subsequently described in [3] In both papers, the relative placement of the storage elements is assumed to be fixed. Algorithms for scheduling local clocks to improve the tolerance of a circuit to process parameter variations are described in ....

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J. P. Fishburn. Clock skew optimization. IEEE Trans. on Computers, 39(7):945--951, July 1990.

....tolerance to delay variations improved by at least 11 . Retiming has been investigated for a variety of clocking disciplines [7, 9, 10, 15] delay models [8, 16] and optimization objectives [1, 4, 12, 14] A linear programming formulation of the clock scheduling problem was first described in [5]. The combined application of retiming and clock scheduling was discussed in [11] A two step procedure for maximizing the operating frequency of a synchronous circuit by combining retiming with clock scheduling was proposed in [2] That work is concerned only with setup violations, however, and ....

....expanded solution space resulting when both setup and hold constraints are considered. The main challenge with the integration of retiming and clock scheduling is the formulation of the problem as a conjunction of linear constraints. As is the case with other i 7 6 3 1 5 1 j k (a) s(j) 0 0 [ 5,6] [ 2,4] i 7 6 3 1 5 1 j k (b) s(j) 0 0 [ 2,7] 1,7] Figure 1. a) Original and (b) retimed circuit. retiming problems [8, 16] the co existence of setup and hold constraints introduces disjunctions among constraints. Thus, the resulting solution space precludes the application of powerful ....

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J. P. Fishburn. Clock skew optimization. IEEE Trans. on Computers, 39(7):945--951, July 1990.

....lines was used to control all the I O registers. All measurements were made using 2 16 random vectors as well as a set of 16 operands that produce the toggle of almost all the output pins. The second type of data facilitated the detection of phenomena like double clocking and zero clocking [28]. The prototypes operated as fast as fine grain pipelines, but using 28 registers instead of 278. Considering the nature of FPGAs, this reduction is not significant in terms of chip size, but definitely affects the latency achieved. The highest operational frequency band (measured) for the ....

J. Fishburn, "Clock Skew Optimization", IEEE Trans. on Computers, Vol. 39, No. 7, pp. 945-951, July 1990. Fig. 4: XC4005 wave pipeline array multiplier layout (intentionally skewed clock version).

....have been usually investigated separately. Retiming has been investigated for a variety of clocking disciplines [7, 9, 10, 14] delay models [8, 15] and optimization objectives [1, 4, 11, 13] A linear programming formulation of the clock scheduling problem was first described by Fishburn in [5]. A two step procedure for maximizing the operating frequency of a synchronous circuit by combining retiming with clock scheduling was proposed in [2] That work considers only setup violations, however. The remainder of this paper has six sections. Section 2 demonstrates the performance gains ....

....and maximum propagation delay of the signals through the corresponding node. The pair [x; y] next to each register represents the permissible clock skew range [12] associated with each combinational data path that terminates at that register. 4 7 4 9 2 2 1 1 0 1 0 1 [0,0] 4,1] 10, 2] [ 11,5] [ 2, 3] 3,4] a) c) 2 9 (b) A B C D E F G 4 7 4 9 2 2 1 1 0 1 [0,0] 4,1] 8,0] 11,5] 3,4] 0 1 2 9 [ 2, 2] A B C D E F G 4 7 4 9 2 2 1 1 0 1 [0,0] 4,1] 11,5] 3,4] 0 1 2 9 [ 8,0] 2, 1] A B C D E F G Figure 1: a) Original circuit. b) Fastest retimed ....

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J. P. Fishburn. Clock skew optimization. IEEE Trans. on Computers, 39(7):945--951, July 1990.

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J. P. Fishburn, "Clock skew optimization," IEEE Transactions on Computers, vol. 39, pp. 945--951, July 1990.

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J. P. Fishburn, "Clock skew optimization," IEEE Transactions on Computers, vol. 39, pp. 945--951, July 1990.

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J. P. Fishburn, "Clock skew optimization," IEEE Transactions on Computers, vol. 39, pp. 945--951, July 1990.

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J. P. Fishburn, "Clock skew optimization," IEEE Trans. Comput., vol. 39, pp. 945--951, 1990.

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J. P. Fishburn, "Clock skew optimization", IEEE Trans. Comput., vol 39, pp 945-951, July, 1990.

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J. P. Fishburn, "Clock skew optimization", IEEE Trans. Comput., vol 39, pp 945-951, July, 1990.

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J. P. Fishburn, "Clock Skew Optimization," IEEE Transactions on Computers, Vol. 39, No. 7, pp. 945-951, July 1990.

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J. P. Fishburn, "Clock Skew Optimization," IEEE Transactions on Computers, vol. 39, pp. 945--951, July 1990.

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J. P. Fishburn. Clock skew optimization. IEEE Trans. on Computers, 39(7):945--951, July 1990.

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