J. Cong and C.-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," Proc. IEEE Intl. Symp. on Circuits and Systems, Vol 1, Apr. 1995, pp. 215--218.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....a smaller clock period and that can be realized with the wire length at least comparable to or smaller than that of a zero skew clock tree. Many clock tree algorithms have been proposed to reduce the wire length and power consumption under the framework of zero skew [2, 3, 4, 9, 10] bounded skew [6, 7, 12], useful skew [21, 22] and associative skew [5] However, they did not fully utilize the flexibility of clock schedule. The flexibility is utilized to improve the circuit performance by combining the retiming in [16] and to improve the circuit reliability in [14] However, the realization of a ....

J. Cong and C. K. Koh. Minimum-cost bounded-skew clock routing. In Proc. ISCAS 95, volume 1, pages 215--218, 1995.

.... subject to a given delay constraint [81] Wire and driver sizing may be combined to reduce the interconnect delay with only a small increase in the power dissipation [15] Clock trees may be constructed that minimize the load on the clock drivers subject to meeting a tolerable clock skew [16] [27] 5.2.5 Circuit Design At the circuit level, power savings techniques that recycle the signal energies using the adiabatic switching principles rather than dissipating them as heat are promising in certain applications where speed can be traded for lower power [2] Similarly, techniques ....

J. Cong and C-K. Koh. " Minimum-cost bounded-skew clock routing. " In Proceedings of the International Symposium on Circuits and Systems, pages 215-218, 1995.

....in terms of total wirelength (i.e. sum of the edge lengths in the tree) thereby increasing circuit area and clock tree capacitance. Thus, the ideal clock tree routing algorithm would produce a zero skew clock tree with minimal total wirelength. This problem, well studied in the VLSI community [15, 8, 10, 9, 24, 18, 25, 6, 16, 21, 7], is precisely the following variant of the classical Steiner tree problem: Find a Steiner tree, with a distinguished root, so that the lengths of all the root leaf paths are the same and the sum of the length of edges in the tree is minimized. # A preliminary version of this paper appeared in ....

J. Cong and C.-K. Koh. Minimum-cost bounded-skew clock routing. TR-950003, University of California, Los Angeles, Computer Science Department, 1995. 13

....Cambridge, MA 02139. Email: amits theory.lcs.mit.edu. This work was done while the author was visiting IBM Almaden Research Center. Also spported in part by a DOD NDSEG fellowship and DARPA grant DABT63 96 C 0018. with minimal total wirelength. This problem, well studied in the VLSI community [15, 8, 10, 9, 24, 18, 25, 6, 16, 21, 7], is precisely the following variant of the classical Steiner tree problem: Find a Steiner tree, with a distinguished root, so that the lengths of all the root leaf paths are the same and the sum of the length of edges in the tree is minimized. While there are many proposed heuristics for ....

J. Cong and C.-K. Koh. Minimum-cost bounded-skew clock routing. TR-950003, University of California, Los Angeles, Computer Science Department, 1995.

....in terms of total wirelength (i.e. sum of the edge lengths in the tree) thereby increasing circuit area and clock tree capacitance. Thus, the ideal clock tree routing algorithm would produce a zero skew clock tree with minimal total wirelength. This problem, well studied in the VLSI community [15, 8, 10, 9, 24, 18, 25, 6, 16, 21, 7], is precisely the following variant of the classical Steiner tree problem: Find a Steiner tree, with a distinguished root, so that the lengths of all the root leaf paths are the same and the sum of the length of edges in the tree is minimized. A preliminary version of this paper appeared in ....

J. Cong and C.-K. Koh. Minimum-cost bounded-skew clock routing. TR-950003, University of California, Los Angeles, Computer Science Department, 1995. 13

....variant is Greedy DME [9] ffl More recently, it has been noted that exact zero skew comes at the price of increased wiring area and higher power dissipation, even as circuits still operate correctly within some non zero skew bound. Hence, the bounded skew tree (BST) problem was addressed in [14, 7, 16, 6]. The BST problem provides a continuous tradeoff between two classic routing problems the zero skew tree (ZST) problem for skew bound B = 0, and the rectilinear Steiner minimum tree (RSMT) problem for B = ffl Finally, Friedman and coauthors have pointed out that the classic zero skew ....

J. Cong and C.-K. Koh, "Minimum-cost bounded-skew clock routing", Proc. IEEE Intl. Symp. Circuits and Systems, volume 1, pp. 215--218, April 1995.

....to minimize the maximum or critical delay of the net. Another category of problems closely related to performancedriven routing is clock routing, which aims at reducing the maximum delay skew among sinks of a net. There have been numerous approaches for zero skew solutions[9, 11] recent work by [3, 4] extends the existing methods to address the bounded skew problem. Most of these existing performance driven and clock routing algorithms are in fact pre routing methods which have several limitations: 1. The optimal routing topology for each net is constructed individually without considering its ....

J. Cong and C. K. Koh, "Minimum-Cost BoundedSkew Clock Routing", Proc. ISCAS 95, 1995.

....and a library of clock buffers with s different size clock buffers and frequency divider doublers, find an optimal level of frequency doublers and clock buffers with proper sizes and wire widths that optimizes the power dissipation and skew sensitivity. 8 Bounded Skew Steiner Tree The methods of [CK95] called DME (Deferred Merge Embedding) algorithm consists of two stages. In a bottom up phase, a tree of merging segments is constructed that represents loci of possible placements of internal nodes (or Steiner points) i na zero skew tree and in a topdown phase, a tree is embedded determining ....

J. Cong and C. K. Koh. "Minimum-Cost Bounded-Skew Clock Routing". In International Symposium on Circuits and Systems, pages 215--218, 1995.

....Skew Routing Tree (BST) Problem: Given a set S = fs 1 ; s ng ae R 2 of sink locations and a skew bound B, find a routing topology G and a minimum cost clock tree TG (S) that satisfies skew(TG (S) B. 1.1. The Extended DME Algorithm The BST problem has been previously addressed in [16] [11], 9] Their basic method, called the Extended DME (Ex DME) algorithm, extends the DME algorithm of [3] 6] 5] 12] via the enabling concept of merging region, which is a set of embedding points with feasible skew and minimum merging cost if no detour wiring occurs 1 . For a fixed tree ....

....in constructing a bounded skew tree: i) a bottom up phase to construct a binary tree of merging regions which represent the loci of possible embedding points of the internal nodes, and (ii) a top down phase to determine the exact locations of the internal nodes. The reader is referred to [11], 16] 9] 10] for more details (the latter is available by anonymous ftp) In the remainder of this subsection, we sketch several key concepts from [11] 16] 9] Let max t(p) and min t(p) denote the maximum and minimum delay values (max delay and min delay, for short) from point p to all ....

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J. Cong and C.-K. Koh. Minimum-cost bounded-skew clock routing. In Proc. IEEE Intl. Symp. Circuits and Systems, volume 1, pages 215--218, April 1995.

....(S) that satisfies skew(T G (S) B. 1 This work was supported by a grant from Cadence Design Systems. A. B. Kahng is currently Visiting Scientist (on sabbatical leave from UCLA) and C. W. A. Tsao is Senior Member of Technical Staff, at Cadence. The BST problem has been previously addressed in [12, 4, 3]. The basic Extended DME (Ex DME) approach extends the DME algorithm [2, 5] via the concept of a merging region, which is a set of embedding points with feasible skew and minimum merging cost if no detour wiring occurs. For a fixed tree topology, Ex DME follows the 2 phase approach of the DME ....

....constructing a bounded skew tree: i) a bottom up phase to construct a binary tree of merging regions which represent the loci of possible embedding points of the internal nodes, and (ii) a top down phase to determine the exact locations of the internal nodes. We now review necessary concepts from [4, 12, 3]. For a node v 2 G with children a and b, its merging region, denoted mr(v) is constructed from the so called joining segments L a 2 mr(a) and L b 2 mr(b) which are the closest boundary segments of mr(a) and mr(b) In practice, L a and L b are either a pair of parallel Manhattan arcs (i.e. ....

J. Cong and C.-K. Koh, "Minimum-cost bounded-skew clock routing", Proc. IEEE Intl. Symp. Circuits and Systems, volume 1, pp. 215--218, April 1995.

No context found.

J. Cong and C.-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," Proc. IEEE Intl. Symp. on Circuits and Systems, Vol 1, Apr. 1995, pp. 215--218.

No context found.

J. Cong and C.-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," UCLA Computer Science Department Technical Report #950003, January 1995.

....as bounded radius bounded cost trees [10] AHHK trees [1] maximum performance trees [8] A trees [15] low delay trees [4] and IDW CFD trees [19] have been proposed to optimize general nets. For clock nets, zero skew tree (ZST) construction [3, 5, 17] and bounded skew tree (BST) construction [13, 20, 11] have been studied extensively. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in [15, 16, 9, 24, 21] can minimize interconnect delay by optimally assigning different wire width to each wire segment in the interconnect design. Both interconnect ....

.... Delta ; w E n g such that the performance measure t T (D;W ) is optimized. The performance measure t T (D;W ) evaluate the signal delay of the net from the source to one or several critical sinks, and it is expressed as a linear combination of the signal delays from the source to all sinks [16, 13, 4]: t T (D;W ) 1im l N i Delta t N i T (D;W ) 1) where l N i measures the criticality of sink N i and t N i T (D;W ) is the signal delay from the source driver D 1 to sink N i in the buffered tree T . Note that we use t T without superscript to denote the weighted sum of delay and t ....

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J. Cong and C.-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," Proc. IEEE Int'l Symp. on Circuits and Systems, Apr. 1995, vol. 1, pp. 215--218.

....the distance d(l(vk) q) is minimized. Note that jev i j may not be equal to d(l(vk ) q) 3.3 Properties of BST DME Algorithm We can show the following results for our BST DME algorithm. The proofs of these results are omitted due to page limitation. They are available in our technical report [5]. Non overlapping Property: In each iteration, the SDFRs of the roots of the trees are non overlapping, and only the boundaries of the SDFRs may touch each other. Octilinear Property: Each feasible region is an octilinear convex polygon. The boundary of the region is defined by octilinear line ....

J. Cong and C.-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," UCLA Computer Science Department Technical Report #950003, January 1995.

No context found.

J. Cong and C.-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," UCLA Computer Science Department Technical Report #950003, January 1995.

.... single layer (planar) constructions [18, 15, 16] A detailed review of clock tree and Steiner routing algorithms is given in [14] In practice, circuits will operate correctly within a given skew tolerance, and indeed exact zero skew is never an actual design requirement [14] Two recent works [8, 12] have addressed the bounded skew routing tree (BST) problem, and proposed clock and Steiner global routing algorithms that construct BSTs under the linear, i.e. pathlength, delay model. The enabling concept in [8, 12] is that of a merging region, which generalizes the merging segment concept of ....

.... exact zero skew is never an actual design requirement [14] Two recent works [8, 12] have addressed the bounded skew routing tree (BST) problem, and proposed clock and Steiner global routing algorithms that construct BSTs under the linear, i.e. pathlength, delay model. The enabling concept in [8, 12] is that of a merging region, which generalizes the merging segment concept of [1, 4, 10] for zeroskew clock trees. 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 7000 0 50 100 150 200 250 HSPICE Skew (ps) Pathlength Skew ( m) 3 3 3 3 3 3 3 3 3 0 100 200 300 400 500 600 0 100 200 300 400 ....

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J. Cong and C.-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," Proc. IEEE Intl. Symp. on Circuits and Systems, Vol 1, Apr. 1995, pp. 215--218.

.... Elmore delay model [Ts91, BoKa92, ChHH92a, ChHH92b] The Deferred Merge Embedding (DME) algorithm by [BoKa92, ChHH92a, Ed91] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Ed93a] The methods in [CoKo95, HuKT95, CoKK95] address the bounded skew tree (BST) construction problem under the pathlength and Elmore delay models by extending the DME algorithm for zero skew tree to BST DME algorithms by the enabling concept of a merging region, which generalizes the merging segment concept of [BoKa92, ChHH92a, Ed91] for ....

....and Elmore delay models. In practice, bounding pathlength skew does not provide reliable control of actual delay skew [CoKK95] For example, Figure 25(a) plots HSPICE delay skew against pathlength delay skew for routing trees generated by the Greedy BST DME algorithm under pathlength delay [CoKo95, HuKT95] on MCNC benchmark circuit r3 [Ts91] Not only is the correlation poor, but the pathlength based BST solutions simply cannot meet tight skew bounds (of 100ps or less) On the other hand, Figure 25(b) demonstrates the accuracy and fidelity of Elmore delay skew to actual skew for routing trees ....

[Article contains additional citation context not shown here]

J. Cong and C.-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," Proc. IEEE Int'l Symp. on Circuits and Systems, Apr. 1995, vol. 1, pp. 215--218.

No context found.

J. Cong and C-K. Koh. " Minimum-cost bounded-skew clock routing. " In Proceedings of the International Symposium on Circuits and Systems, pages 215-218, 1995.

No context found.

J. Cong and C-K. Koh. " Minimum-cost bounded-skew clock routing. " In Proceedings of the International Symposium on Circuits and Systems, pages 215-218, 1995.

No context found.

J. Cong and C.-K. Koh. Minimum-cost bounded-skew clock routing. TR-950003, University of California, Los Angeles, Computer Science Department, 1995.

No context found.

J. Cong and C-K Koh, "Minimum-Cost Bounded-Skew Clock Routing ", to appear in Proc. Int'l Symposiumon Circuits and Systems, May 1995.

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