Y. P. Chen and D.F. Wong, "An algorithm for zero-skew clock tree routing with buffer insertion", Proc. European on Computer-Aided Design, pp.219-223, 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....at Charlotte, NC 28223 2 Department of Electronic Engineering Fudan University, Shanghai 200433, China. This research is supported in part by AirForce Office of Scientific Research grant F49620 96 1 0341 2 as shown by our optimal buffer position theory in this paper. Algorithms proposed in [9,10,11] insert the same number of buffers in each source to sink paths. They further assume the buffers at the same level have the same size. Undoubtedly this buffer insertion strategy helps to reduce skew sensitivity to process variations[12] but this strategy requires an almost balanced routing tree ....

Y. P. Chen and D.F. Wong, "An algorithm for zero-skew clock tree routing with buffer insertion", Proc. European on Computer-Aided Design, pp.219-223, 1994.

....Synthesis Finally, we extend our bounded skew routing method to handle the practical case of buffering hierarchies in large circuits. There have been many works on buffered clock tree designs. 25] 21] 8] determine the buffer tree hierarchy for the given clock tree layout or topology. 23] [7] design the buffer tree hierarchy and the routing of the clock net simultaneously. However, the prevailing design methodology for clock tree synthesis is that the buffer tree hierarchy is pre designed before the physical layout of the clock tree (e.g. see recent vendor tools for automatic buffer ....

.... Delta Gamma k 0 to represent a buffer hierarchy with k i buffers at level i, 0 i M . For example, a 170 16 4 1 hierarchy has 170 buffers at level 3, 16 buffers at level 2, etc. Note that we always have k 0 = 1 since there is only one buffer at the root of the clock tree. As in [8] 21] [7], to minimize the skew induced by the changes of buffer sizes due to the process variation, we assume that identical buffers are used at the same buffer level. From the discussion of our method below, we can see that our method can work without this assumption by minor modification. We propose ....

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Y. P. Chen and D. F. Wong. An algorithm for zeroskew clock tree routing with buffer insertion. In Proc. European Design and Test Conf., pages 652-- 657, 1996.

....to balance delays, a buffer can be inserted. As the feature size becomes smaller, this approach has become more attractive and less expensive in terms of chip area. The earlier works by [DhFW84, WuSh92] considered insertion of uniform size buffers in a H tree structure. The more recent works by [ViMa95, ChWo96] perform buffer insertion simultaneously with clock routing. The work on buffer insertion and sizing will be presented in Section 5.4.3. The work on buffer insertion and wiresizing will be presented in Section 5.4.4. The algorithm proposed by Dhar, Franklin, and Wann [DhFW84] inserts buffers into ....

....paths have equal number of buffers inserted along the path. Moreover, buffers at the same level have the same size. These restrictions may affect the optimality in terms of signal delay and total wirelength. However, they help to reduce skew sensitivity to process variations. Chen and Wong [ChWo96] also considered buffer insertion and topology generation simultaneously. Instead of considering buffer insertion at each merging step as in the GRIN algorithm, ChWo96] considers inserting buffers at the roots of all subtrees. Starting with a set S of subtrees, the algorithm performs several ....

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Y. P. Chen and D. F. Wong, "An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion," Proc. European Design and Test Conf., 1996.

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