T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst., vol. 39, pp. 799--814, Nov. 1992.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....skew, sharp edges and the optimal use of routing resources. In addition, it is also important to reduce the total propagation delay through the network. Traditionally, clock networks have been designed as tree structures since these are considered to be easier to optimize, and various algorithms [2, 17] for constructing zero skew clock trees under the Elmore delay metric have been explored in the past. Several delay skew minimization techniques [8, 9] and the wire width optimization techniques [12, 13] have been proposed. As compared to tree structures, clock meshes are known to potentially ....

T. Chao, et al., "Zero Skew Clock Routing With Minimum Wirelength", IEEE Transactions on Circuits and Systems, vol. 39, pp. 799-814, Nov. 1992.

.... is called zero clock skew scheduling and is implemented in many different ways such as inserting distributed buffers within the clock tree [2] using symmetric distribution networks, such as H tree structures [3] to minimize the clock skew, and applying zero skew clock routing algorithms [4, 5] to automatically layout high speed clock distribution networks. Minimum (or zero) clock skew scheduling has been used in many high performance circuits. Intel Corporation applies a minimum clock skew methodology with localized tuning in the design of their latest microproces sors, including the ....

T- H. Chao, Y.-C. Hsu, J. M. He, K. D. Boese, and A. B. Kahng. "Zero Skew Clock Routing with Minimum Wirelength. " IEEE Transactions Circuits Systems 11: Analog and Digital Signal Processing, Vol. 39, No. 11, pp. 799814, November 1992.

....a clock schedule that achieves a smaller clock period and that can be realized with the wire length at least comparable to or smaller than that of a zero skew clock tree. Many clock tree algorithms have been proposed to reduce the wire length and power consumption under the framework of zero skew [2, 3, 4, 9, 10], bounded skew [6, 7, 12] useful skew [21, 22] and associative skew [5] However, they did not fully utilize the flexibility of clock schedule. The flexibility is utilized to improve the circuit performance by combining the retiming in [16] and to improve the circuit reliability in [14] ....

T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahgn. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circuits and Systems, 39(11):799-- 814, 1992.

....interconnects has a major effect on the skew of the clock signal net. The goal of the clock signal distribution network is to maintain a zero (or near zero) skew through it. To ensure zero skew clock distribution, a symmetric H Tree structure or a bottom up merging technique can be used [26], 27] For simplicity and without loss of generality, for our analysis we consider the H Tree clock topology consisting of trunks (vertical stripes) and branches (horizontal stripes) as depicted in Figure 10. In general, the top level segments of the tree are wider than the lower level segments. ....

....symmetry cannot guarantee the zero skew. If, for example, trunk 1 experiences a nonuniform thermal profile, the clock driver must be connected to this segment at a place other than the center of the segment. This also suggests that during a bottom up binary merge construction of the clock tree [26], the actual temperature dependent delay must be considered. Having more than a 30 C thermal gradient in some designs, justifies the importance of this kind of analysis. Notice that we consider the steadystate thermal profile of the substrate. Even though the dynamic behavior of the chip causes ....

T.H. Chao, Y.C. Hsu, J.M. Ho, K.D. Boese, A.B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Transaction on Circuits andSystems-II, vol. 39, No. 11, pp. 799-814, 1992.

....through the use of an activity driven clock tree. Fig. 1 shows an example of gated clock tree. Work on clock trees has focused on zero or near zero skew routing [4] 6] 13] 21] In addition to zero skew, further work concentrates on routing clock trees with minimal total wire length [3] [7], 8] The construction of clock trees that minimize phase delay of the clock signal has been studied in [5] and [9] Work on buffered clock trees has focused on minimizing the phase delay of the clock tree [20] More recently, work in [17] considers the minimization of skew and delay in the ....

T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst., vol. 39, pp. 799--814, Nov. 1992.

....be obtained by radius minimization, with direct paths between the driver and all sink nodes. Shortest path trees rooted at the source achieve this goal. A number of works address the radius objectives, both for general path length minimization, and also for skew minimization in clock nets [3] [6], 13] 20] A minimum radius construction with a suitable root point may be also be a minimum diameter construction. When there are multiple sources and sinks, path length minimization can be achieved by minimizing the maximum distance between any pair of nodes, which leads to diameter o ....

....contain the rectangle. connecting the center of the circle to each point in the set was shown to have the minimum diameter possible of any Steiner tree over the points. We follow their general approach, but address the Manhattan plane and also pursue tree length minimization. The work in [3] [6], 13] and [20] can be used to construct minimum diameter trees, but they are concerned mainly with skew minimization instead of total tree length minimization. The Manhattan minimum diameter Steiner tree problem has not been explicitly studied in the literature. Our work studies the construction ....

T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst. , vol. 39, pp. 799--814, Nov. 1992.

....activity through the use of an activity driven clock tree. Fig.1 shows an example of gated clock tree. Work on clock trees has focused on zero or near zero skew routing [4] 6] 13] 21] In addition to zero skew, further work concentrates on routing clock trees with minimal total wire length [7], 3] 8] The construction of clock trees that minimize phase delay of the clock signal has been studied in [5] 9] Work on buffered clock trees has focused on minimizing the phase delay of the clock tree [20] More recently, work in [17] considers the minimization of skew and delay in the ....

T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B.Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems, vol. 39, no. 11, pp. 799-814, 1992.

....To achieve synchronicity, the skew should be zero. This is a significant issue in VLSI design, as non zero clock skew has been estimated to account for over 10 of overall system cycle time in some high performance systems [4] Though it is easy to produce zero skew clock routing trees (see e.g. [5]) naive algorithms may produce trees that are expensive in terms of total wirelength (i.e. sum of the edge lengths in the tree) thereby increasing circuit area and clock tree capacitance. Thus, the ideal clock tree routing algorithm would produce a zero skew clock tree with minimal total ....

....model is presented in [22, 23] The zero skew is obtained by a bottom up hierarchical approach via a zero skew merging of the recursive solutions. The main emphasis is on experimental results. A two step approach to obtaining zero skew while simultaneously minimizing wirelength is pioneered in [5]. In this, the authors present the Deferred Merge Embedding (DME) algorithm, which embeds any given connection topology to create a zero skew clock tree. The wirelength is optimal for linear delay. The connection topology is generated by a top down balanced bipartition (BB) approach. Though the ....

T-H. Chao, Y-C. Hsu, J-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circuits and Systems --- II: Analog and Digital Signal Processing, 39(11):799--814, 1992.

.... is not known for a fixed tree topology the problem can be solved in linear time by using the Deferred Merge Embedding (DME) algorithm independently introduced in [6, 7, 11] Although the rectilinear zero and bounded skew tree problems have received much attention in the VLSI CAD literature [4, 6, 7, 8, 10, 11, 12, 16, 17, 20] (see Chapter 4 of [18] 2 for a detailed review) the first algorithms with constant approximation factors have been proposed only recently, by Charikar et al. 9] They give algorithms with approximation factors of 2e 5:44 and 16.86 for ZST and BST problems, respectively. The BST algorithm in ....

CHAO, T.-H., HSU, Y.-C., HO, J.-M., BOESE, K., AND KAHNG, A. Zero skew clock routing with minimum wirelength. IEEE Transactions on Circuits and Systems --- II: Analog and Digital Signal Processing 39 (1992), 799--814.

.... T pd T su T skew : Time TD Q is the time from the clock edge that captures the data to the time the data is available at the output of the register. Time T pd is the maximum delay through the combinational block. Obviously minimizing clock skew is the most important task of clock routing [Bak90, CHHBK92, Eda93, JSK90, KCR91, Tsa91]. In most cases, clock nets are routed as binary trees. We assume this is the case. Therefore, we also call clock nets as clock trees. CL D1 Q1 D2 Q2 Clock Source T skew C1 C2 Figure 1.7: An example of clock skew. In addition to clock skew, signal delay and wirelength are also important ....

....by clock signals. The clock frequency determines the performance of a circuit. Clock skew, defined as the maximum arrival time difference from the clock source to sinks, can degrade the clock frequency significantly. Therefore, minimizing clock skew is the most important task of clock tree routing [Bak90, CHHBK92, Eda93, JSK90, KCR91, Tsa91]. In addition to clock skew, signal delay and wirelength are also important object functions to be minimized, as in general net routing problem. Clock signal delay is also called phase delay. It appears as inter chip skew and affects system performance, which was pointed out in [JSK90] Long wire ....

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T. Chao, Y. Hsu, J. Ho, K.D. Boose and A.B. Kahng, " Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems 39(11), pp.799-814, 1992. 112

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CHAO, T.-H., HSU, Y.-C. H., HO, J.-M., BOESE, K. D., AND KAHNG, A. B. 1992. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circ. and Syst. 39, 11 (Nov.) 799 -- 814.

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T.-H. Chao, Y.-C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With MinimumWirelength," IEEE Trans. on Circuits and Systems 39(11), Nov. 1992, pp. 799--814.

....on both performance and power dissipation. Thus, the zero skew clock tree and performance driven routing literatures have seen rapid growth over the past several years; see Kahng and Robins [1994] for a detailed review. Recent works have accomplished exact zero skew under the Elmore delay model [Chao et al. 1992b; Edahiro 1993a; Tsay 1993] The Deferred Merge Embedding (DME) algorithm by Chao et al. 1992b] and Edahiro [1992] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Edahiro 1993a] Recent works ....

....routing literatures have seen rapid growth over the past several years; see Kahng and Robins [1994] for a detailed review. Recent works have accomplished exact zero skew under the Elmore delay model [Chao et al. 1992b; Edahiro 1993a; Tsay 1993] The Deferred Merge Embedding (DME) algorithm by Chao et al. 1992b] and Edahiro [1992] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Edahiro 1993a] Recent works have also given new methods for single layer (planar) clock routing [Kahng and Tsao 1996; Zhu ....

[Article contains additional citation context not shown here]

CHAO, T.-H., HSU, Y.-C. H., HO, J.-M., BOESE, K. D., AND KAHNG, A. B. 1992. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circ. and Syst. 39, 11 (Nov.) 799 -- 814.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst., vol. 39, pp. 799--814, Nov. 1992.

No context found.

T.-H. Chao, Y.-C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems, 39(11), Nov. 1992, pp. 799--814.

No context found.

T.-H. Chao, Y.-C. Hsu, J.-M. Ho, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst. II, vol. 39, pp. 799--814, Nov. 1992.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero Skew Clock Routing with Minimum Wirelength", IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. CAS-39, No. 11, pp. 799-814, November, 1992.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst. II, vol. 39, pp. 799--814, 1992.

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T.-H. Chao, Y.-C. Hsu, J.-M Ho, and A. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst. II, vol. 39, pp. 799--814, Nov. 1992.

No context found.

Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho, and A.B. Kahng. Zero skew clock routing with minimum wirelength. Circuits and Systems II: Analog and Digital Signal Processing, Volumn 39, Issue 11:799--814, Nov. 1992.

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Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho, and A.B. Kahng. Zero skew clock routing with minimum wirelength. Circuits and Systems II: Analog and Digital Signal Processing, Volumn 39, Issue 11:799--814, Nov. 1992.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, A. B. Khang, "Zero Skew Clock Routing with Minimum Wirelength," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 39, No. 11, pp. 799-814, November 1992.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Transactions on Circuits and Systems - Analog and Digital Signal Processing, 39(11):799--814, November 1992.

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T.- H. Chao, Y.-C. Hsu, J. -M. Ho, K. D. Boese, and A. B. Kahng. "Zero Skew Clock Routing with Minimum Wirelength, " IEEE Transactions Circuits Systems II: Analog and Digital Signal Processing, Vol. 39, No. 11, pp. 799-814, November 1992.

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T. Chao, et al., "Zero Skew Clock Routing with Minimum Wirelength," IEEE Trans. Circuits Syst.-II, vol. 39, no. 11, pp. 799-814, Nov. 1992.

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