T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst., vol. 39, pp. 799--814, Nov. 1992.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....skew, sharp edges and the optimal use of routing resources. In addition, it is also important to reduce the total propagation delay through the network. Traditionally, clock networks have been designed as tree structures since these are considered to be easier to optimize, and various algorithms [2, 17] for constructing zero skew clock trees under the Elmore delay metric have been explored in the past. Several delay skew minimization techniques [8, 9] and the wire width optimization techniques [12, 13] have been proposed. As compared to tree structures, clock meshes are known to potentially ....

T. Chao, et al., "Zero Skew Clock Routing With Minimum Wirelength", IEEE Transactions on Circuits and Systems, vol. 39, pp. 799-814, Nov. 1992.

.... is called zero clock skew scheduling and is implemented in many different ways such as inserting distributed buffers within the clock tree [2] using symmetric distribution networks, such as H tree structures [3] to minimize the clock skew, and applying zero skew clock routing algorithms [4, 5] to automatically layout high speed clock distribution networks. Minimum (or zero) clock skew scheduling has been used in many high performance circuits. Intel Corporation applies a minimum clock skew methodology with localized tuning in the design of their latest microproces sors, including the ....

T- H. Chao, Y.-C. Hsu, J. M. He, K. D. Boese, and A. B. Kahng. "Zero Skew Clock Routing with Minimum Wirelength. " IEEE Transactions Circuits Systems 11: Analog and Digital Signal Processing, Vol. 39, No. 11, pp. 799814, November 1992.

....a clock schedule that achieves a smaller clock period and that can be realized with the wire length at least comparable to or smaller than that of a zero skew clock tree. Many clock tree algorithms have been proposed to reduce the wire length and power consumption under the framework of zero skew [2, 3, 4, 9, 10], bounded skew [6, 7, 12] useful skew [21, 22] and associative skew [5] However, they did not fully utilize the flexibility of clock schedule. The flexibility is utilized to improve the circuit performance by combining the retiming in [16] and to improve the circuit reliability in [14] ....

T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahgn. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circuits and Systems, 39(11):799-- 814, 1992.

....interconnects has a major effect on the skew of the clock signal net. The goal of the clock signal distribution network is to maintain a zero (or near zero) skew through it. To ensure zero skew clock distribution, a symmetric H Tree structure or a bottom up merging technique can be used [26], 27] For simplicity and without loss of generality, for our analysis we consider the H Tree clock topology consisting of trunks (vertical stripes) and branches (horizontal stripes) as depicted in Figure 10. In general, the top level segments of the tree are wider than the lower level segments. ....

....symmetry cannot guarantee the zero skew. If, for example, trunk 1 experiences a nonuniform thermal profile, the clock driver must be connected to this segment at a place other than the center of the segment. This also suggests that during a bottom up binary merge construction of the clock tree [26], the actual temperature dependent delay must be considered. Having more than a 30 C thermal gradient in some designs, justifies the importance of this kind of analysis. Notice that we consider the steadystate thermal profile of the substrate. Even though the dynamic behavior of the chip causes ....

T.H. Chao, Y.C. Hsu, J.M. Ho, K.D. Boese, A.B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Transaction on Circuits andSystems-II, vol. 39, No. 11, pp. 799-814, 1992.

....through the use of an activity driven clock tree. Fig. 1 shows an example of gated clock tree. Work on clock trees has focused on zero or near zero skew routing [4] 6] 13] 21] In addition to zero skew, further work concentrates on routing clock trees with minimal total wire length [3] [7], 8] The construction of clock trees that minimize phase delay of the clock signal has been studied in [5] and [9] Work on buffered clock trees has focused on minimizing the phase delay of the clock tree [20] More recently, work in [17] considers the minimization of skew and delay in the ....

T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst., vol. 39, pp. 799--814, Nov. 1992.

....be obtained by radius minimization, with direct paths between the driver and all sink nodes. Shortest path trees rooted at the source achieve this goal. A number of works address the radius objectives, both for general path length minimization, and also for skew minimization in clock nets [3] [6], 13] 20] A minimum radius construction with a suitable root point may be also be a minimum diameter construction. When there are multiple sources and sinks, path length minimization can be achieved by minimizing the maximum distance between any pair of nodes, which leads to diameter o ....

....contain the rectangle. connecting the center of the circle to each point in the set was shown to have the minimum diameter possible of any Steiner tree over the points. We follow their general approach, but address the Manhattan plane and also pursue tree length minimization. The work in [3] [6], 13] and [20] can be used to construct minimum diameter trees, but they are concerned mainly with skew minimization instead of total tree length minimization. The Manhattan minimum diameter Steiner tree problem has not been explicitly studied in the literature. Our work studies the construction ....

T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst. , vol. 39, pp. 799--814, Nov. 1992.

....activity through the use of an activity driven clock tree. Fig.1 shows an example of gated clock tree. Work on clock trees has focused on zero or near zero skew routing [4] 6] 13] 21] In addition to zero skew, further work concentrates on routing clock trees with minimal total wire length [7], 3] 8] The construction of clock trees that minimize phase delay of the clock signal has been studied in [5] 9] Work on buffered clock trees has focused on minimizing the phase delay of the clock tree [20] More recently, work in [17] considers the minimization of skew and delay in the ....

T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B.Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems, vol. 39, no. 11, pp. 799-814, 1992.

....To achieve synchronicity, the skew should be zero. This is a significant issue in VLSI design, as non zero clock skew has been estimated to account for over 10 of overall system cycle time in some high performance systems [4] Though it is easy to produce zero skew clock routing trees (see e.g. [5]) naive algorithms may produce trees that are expensive in terms of total wirelength (i.e. sum of the edge lengths in the tree) thereby increasing circuit area and clock tree capacitance. Thus, the ideal clock tree routing algorithm would produce a zero skew clock tree with minimal total ....

....model is presented in [22, 23] The zero skew is obtained by a bottom up hierarchical approach via a zero skew merging of the recursive solutions. The main emphasis is on experimental results. A two step approach to obtaining zero skew while simultaneously minimizing wirelength is pioneered in [5]. In this, the authors present the Deferred Merge Embedding (DME) algorithm, which embeds any given connection topology to create a zero skew clock tree. The wirelength is optimal for linear delay. The connection topology is generated by a top down balanced bipartition (BB) approach. Though the ....

T-H. Chao, Y-C. Hsu, J-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circuits and Systems --- II: Analog and Digital Signal Processing, 39(11):799--814, 1992.

.... is not known for a fixed tree topology the problem can be solved in linear time by using the Deferred Merge Embedding (DME) algorithm independently introduced in [6, 7, 11] Although the rectilinear zero and bounded skew tree problems have received much attention in the VLSI CAD literature [4, 6, 7, 8, 10, 11, 12, 16, 17, 20] (see Chapter 4 of [18] 2 for a detailed review) the first algorithms with constant approximation factors have been proposed only recently, by Charikar et al. 9] They give algorithms with approximation factors of 2e 5:44 and 16.86 for ZST and BST problems, respectively. The BST algorithm in ....

CHAO, T.-H., HSU, Y.-C., HO, J.-M., BOESE, K., AND KAHNG, A. Zero skew clock routing with minimum wirelength. IEEE Transactions on Circuits and Systems --- II: Analog and Digital Signal Processing 39 (1992), 799--814.

.... T pd T su T skew : Time TD Q is the time from the clock edge that captures the data to the time the data is available at the output of the register. Time T pd is the maximum delay through the combinational block. Obviously minimizing clock skew is the most important task of clock routing [Bak90, CHHBK92, Eda93, JSK90, KCR91, Tsa91]. In most cases, clock nets are routed as binary trees. We assume this is the case. Therefore, we also call clock nets as clock trees. CL D1 Q1 D2 Q2 Clock Source T skew C1 C2 Figure 1.7: An example of clock skew. In addition to clock skew, signal delay and wirelength are also important ....

....by clock signals. The clock frequency determines the performance of a circuit. Clock skew, defined as the maximum arrival time difference from the clock source to sinks, can degrade the clock frequency significantly. Therefore, minimizing clock skew is the most important task of clock tree routing [Bak90, CHHBK92, Eda93, JSK90, KCR91, Tsa91]. In addition to clock skew, signal delay and wirelength are also important object functions to be minimized, as in general net routing problem. Clock signal delay is also called phase delay. It appears as inter chip skew and affects system performance, which was pointed out in [JSK90] Long wire ....

[Article contains additional citation context not shown here]

T. Chao, Y. Hsu, J. Ho, K.D. Boose and A.B. Kahng, " Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems 39(11), pp.799-814, 1992. 112

.... is not known for a fixed tree topology the problem can be solved in linear time by using the Deferred Merge Embedding (DME) algorithm independently introduced in [6, 7, 11] Although the rectilinear zero and bounded skew tree problems have received much attention in the VLSI CAD literature [4, 6, 7, 8, 10, 11, 12, 16, 17, 20] (see Chapter 4 of [18] for a detailed review) the first algorithms with constant approximation factors have been proposed only recently, by Charikar et al. 9] They give algorithms with approximation factors of 2e 5:44 and 16.86 for ZST and BST problems, respectively. The BST algorithm in [9] ....

CHAO, T.-H., HSU, Y.-C., HO, J.-M., BOESE, K., AND KAHNG, A. Zero skew clock routing with minimum wirelength. IEEE Transactions on Circuits and Systems --- II: Analog and Digital Signal Processing 39 (1992), 799--814.

....by clock signals. The clock frequency determines the performance of a circuit. Clock skew, defined as the maximum arrival time difference from the clock source to sinks, can degrade the clock frequency significantly. Therefore, minimizing clock skew is the most important task of clock tree routing [1, 4, 7, 11, 12, 16]. In addition to clock skew, signal delay and wirelength are also important object functions to be minimized, as in general net routing problem. Clock signal delay is also called phase delay. It appears as inter chip skew and affects system performance, which was pointed out in [11] Long wire ....

....distance) Normally l 1 l 2 = l. If not, then it is implied that the delay and capacitance differences between T v1 and T v2 is large. Hence it is required that either l 1 l and l 2 = 0 or l 1 = 0 and l 2 l. In other words, wire elongation is adopted to balance delay. The DME algorithm[4] makes use of the fact that on each merging, the solution is a diagonal segment instead of a single point. Therefore, the bottom up phase needs only to determine the merging segment ms(v) for each v and defer embedding until the top down phase. In the top down phase, all tree nodes are embedded ....

[Article contains additional citation context not shown here]

T. Chao, Y. Hsu, J. Ho, K.D. Boose and A.B. Kahng, " Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems 39(11), pp.799-814, 1992.

....To achieve synchronicity, the skew should be zero. This is indeed a real issue in VLSI design, as non zero clock skew has been estimated to account for over 10 of overall system cycle time in some highperformance systems [4] Though it is easy to produce zero skew clock routing trees (see e.g. [5]) naive algorithms may produce trees that are expensive in terms of total wirelength (i.e. sum of the edge lengths in the tree) thereby increasing circuit area and clock tree capacitance. Thus, the ideal clock tree routing algorithm would produce a zero skew clock tree with minimal total ....

....model is presented in [22, 23] The zero skew is obtained by a bottom up hierarchical approach via a zero skew merging of the recursive solutions. The main emphasis is on experimental results. A two step approach to obtaining zero skew while simultaneously minimizing wirelength is pioneered in [5]. In this, the authors present the Deferred Merge Embedding (DME) algorithm, which embeds any given connection topology to create a zero skew clock tree. The wirelength is optimal for linear delay. The connection topology is generated by a top down balanced bipartition (BB) approach. Though the ....

T-H. Chao, Y-C. Hsu, J-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circuits and Systems --- II: Analog and Digital Signal Processing, 39(11):799--814, 1992.

....To achieve synchronicity, the skew should be zero. This is a significant issue in VLSI design, as non zero clock skew has been estimated to account for over 10 of overall system cycle time in some highperformance systems [4] Though it is easy to produce zero skew clock routing trees (see e.g. [5]) naive algorithms may produce trees that are expensive in terms of total wirelength (i.e. sum of the edge lengths in the tree) thereby increasing circuit area and clock tree capacitance. Thus, the ideal clock tree routing algorithm would produce a zero skew clock tree Department of Computer ....

....model is presented in [22, 23] The zero skew is obtained by a bottom up hierarchical approach via a zero skew merging of the recursive solutions. The main emphasis is on experimental results. A two step approach to obtaining zero skew while simultaneously minimizing wirelength is pioneered in [5]. In this, the authors present the Deferred Merge Embedding (DME) algorithm, which embeds any given connection topology to create a zero skew clock tree. The wirelength is optimal for linear delay. The connection topology is generated by a top down balanced bipartition (BB) approach. Though the ....

T-H. Chao, Y-C. Hsu, J-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circuits and Systems --- II: Analog and Digital Signal Processing, 39(11):799--814, 1992.

....To achieve synchronicity, the skew should be zero. This is a significant issue in VLSI design, as non zero clock skew has been estimated to account for over 10 of overall system cycle time in some high performance systems [4] Though it is easy to produce zero skew clock routing trees (see e.g. [5]) naive algorithms may produce trees that are expensive in terms of total wirelength (i.e. sum of the edge lengths in the tree) thereby increasing circuit area and clock tree capacitance. Thus, the ideal clock tree routing algorithm would produce a zero skew clock tree with minimal total ....

....model is presented in [22, 23] The zero skew is obtained by a bottom up hierarchical approach via a zero skew merging of the recursive solutions. The main emphasis is on experimental results. A two step approach to obtaining zero skew while simultaneously minimizing wirelength is pioneered in [5]. In this, the authors present the Deferred Merge Embedding (DME) algorithm, which embeds any given connection topology to create a zero skew clock tree. The wirelength is optimal for linear delay. The connection topology is generated by a top down balanced bipartition (BB) approach. Though the ....

T-H. Chao, Y-C. Hsu, J-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circuits and Systems --- II: Analog and Digital Signal Processing, 39(11):799--814, 1992.

.... arrays [1] the method of means and medians (MMM) by [10] the recursive geometric matching method by [6] and exact zero skew routing under the Elmore delay model by [17] Recently, the problem of embedding a given topology on a Manhattan plane with zero path length skew is solved optimally by [2, 7] using the Deferred MergeEmbedding (DME) algorithm. The algorithm can be either applied to a given clock topology [2] or combined with a clock topology generation algorithm to achieve zero skew with smaller wirelength [7] Currently, researches on clock routing are moving along a few directions. ....

....zero skew routing under the Elmore delay model by [17] Recently, the problem of embedding a given topology on a Manhattan plane with zero path length skew is solved optimally by [2, 7] using the Deferred MergeEmbedding (DME) algorithm. The algorithm can be either applied to a given clock topology [2] or combined with a clock topology generation algorithm to achieve zero skew with smaller wirelength [7] Currently, researches on clock routing are moving along a few directions. Zero skew planar routing was first proposed by [18] using Max Min operations and followed up by [12, 13] using ....

[Article contains additional citation context not shown here]

T.-H. Chao, Y.-C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems, 39(11), Nov. 1992, pp. 799--814.

....can be obtained by radius minimization, with direct paths between the driver and all sink nodes. Shortest path trees rooted at the source achieve this goal. A number of works address the radius objectives, both for general path length minimization, and also for skew minimization in clock nets[13, 3, 6, 20]. A minimum radius construction with a suitable root point may be also be a minimum diameter construction. When there are multiple sources and sinks, path length minimization can be achieved by minimizing the maximum distance between any pair of nodes, which leads to diameter minimization. Our ....

....diameter circle, a star topology connecting the center of the circle to each point in the set was shown to have the minimum diameter possible of any Steiner tree over the points. We follow their general approach, but address the Manhattan plane and also pursue tree length minimization. The work in [13, 3, 6, 20] can be used to construct minimum diameter trees, but they are concerned mainly with skew minimization instead of total tree length minimization. The Manhattan minimum diameter Steiner tree problem has not been explicitly studied in the literature. Our work studies the construction of minimum ....

T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero Skew Clock Routing with Minimum Wirelength," IEEE Trans. on Circuits and Systems, Vol. 39, No. 11, pp. 799-814, November 1992.

.... arrays [1] the method of means and medians (MMM) by [10] the recursive geometric matching method by [6] and exact zero skew routing under the Elmore delay model by [17] Recently, the problem of embedding a given topology on a Manhattan plane with zero path length skew is solved optimally by [2, 7] using the Deferred Merge Embedding (DME) algorithm. The algorithm can be either applied to a given clock topology [2] or combined with a clock topology generation algorithm to achieve zero skew with smaller wirelength [7] Currently, research on clock routing is moving along a few directions. ....

....skew routing under the Elmore delay model by [17] Recently, the problem of embedding a given topology on a Manhattan plane with zero path length skew is solved optimally by [2, 7] using the Deferred Merge Embedding (DME) algorithm. The algorithm can be either applied to a given clock topology [2] or combined with a clock topology generation algorithm to achieve zero skew with smaller wirelength [7] Currently, research on clock routing is moving along a few directions. Zero skew planar routing was first proposed by [18] using Max Min operations, followed up by [12, 13] using single phase ....

[Article contains additional citation context not shown here]

T.-H. Chao, Y.-C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems, 39(11), Nov. 1992, pp. 799--814.

....clock skews are used constructively to improve system performance. Clock schedule optimization will be discussed in Section 5.6. Recent works on clock skew minimization have accomplished exact zero skew under both the pathlengthdelay model [BoKa92, Ed91, Ed92] and the Elmore delay model [Ts91, BoKa92, ChHH92a, ChHH92b]. The Deferred Merge Embedding (DME) algorithm by [BoKa92, ChHH92a, Ed91] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Ed93a] The methods in [CoKo95, HuKT95, CoKK95] address the bounded skew ....

....recursion then continues on the subsets S 1 and S 2 . Note that BB is a purely topology generation algorithm. It relies on the embedding algorithm to be presented in Section 5.2 to embed the abstract topology generated. 5.1. 2 Bottom Up Topology Generation In contrast to the top down approaches of [JaSK90, ChHH92b], the KCR geometric matching algorithm was proposed by Kahng, Cong, and Robins [KaCR91, CoKR93] as the first bottom up approach for clock tree abstract topologygeneration. It constructs a routing tree by iteratively joining pairs of subtrees which are close, and can handle cell based design with ....

[Article contains additional citation context not shown here]

T.-H. Chao, Y.-C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With Minimum Wirelength," IEEE Trans. on Circuits and Systems, 39(11), Nov. 1992, pp. 799--814.

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CHAO, T.-H., HSU, Y.-C. H., HO, J.-M., BOESE, K. D., AND KAHNG, A. B. 1992. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circ. and Syst. 39, 11 (Nov.) 799 -- 814.

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T.-H. Chao, Y.-C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With MinimumWirelength," IEEE Trans. on Circuits and Systems 39(11), Nov. 1992, pp. 799--814.

....on both performance and power dissipation. Thus, the zero skew clock tree and performance driven routing literatures have seen rapid growth over the past several years; see Kahng and Robins [1994] for a detailed review. Recent works have accomplished exact zero skew under the Elmore delay model [Chao et al. 1992b; Edahiro 1993a; Tsay 1993] The Deferred Merge Embedding (DME) algorithm by Chao et al. 1992b] and Edahiro [1992] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Edahiro 1993a] Recent works ....

....routing literatures have seen rapid growth over the past several years; see Kahng and Robins [1994] for a detailed review. Recent works have accomplished exact zero skew under the Elmore delay model [Chao et al. 1992b; Edahiro 1993a; Tsay 1993] The Deferred Merge Embedding (DME) algorithm by Chao et al. 1992b] and Edahiro [1992] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Edahiro 1993a] Recent works have also given new methods for single layer (planar) clock routing [Kahng and Tsao 1996; Zhu ....

[Article contains additional citation context not shown here]

CHAO, T.-H., HSU, Y.-C. H., HO, J.-M., BOESE, K. D., AND KAHNG, A. B. 1992. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circ. and Syst. 39, 11 (Nov.) 799 -- 814.

No context found.

T.-H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength", IEEE Trans. Circuits and Systems, 39(11):799--814, November 1992.

....Pathlength Delay Andrew B. Kahng and Chung Wen Albert Tsao UCLA Computer Science Dept. Los Angeles, CA 90024 1596 USA Abstract Clock routing has become a critical issue in the layout design of high performance systems. We show that the two passes (bottom up and top down) of the DME algorithm [2, 3, 4, 8] can be replaced by a single topdown pass, which yields exactly the same (optimal) solution. From this, we develop a top down algorithm which dynamically determines and embeds the clock tree topology, such that (i) the embedding is guaranteed to be planar, and (ii) the result has provably minimum ....

....1 Introduction The placement phase of physical layout determines positions for the synchronizing elements of a circuit, which are the sinks of the clock net. Large cell based designs can have thousands of sinks in a clock net, located arbitrarily throughout the layout region. Following [2, 4], we denote the set of sink locations in a clock routing instance as S = fs 1 ; s 2 ; s ng ae 2 . A connection topology is a rooted binary tree, G, which has n leaves corresponding to the sinks in S. A clock tree T (S) is an embedding of the connection topology in the Manhattan plane, ....

[Article contains additional citation context not shown here]

T.-H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With Minimum Wirelength ", IEEE Trans. on Circuits and Systems 39(11), November 1992, pp. 799-814.

....the merging cost at node v is the sum of the wirelengths of edges sv and tv in such a minimum cost ZST solution. Note that this does not necessarily equal the sum of Manhattan distances d(s; v) d(t; v) since sink delays must be balanced. The following discussion uses the same terminology as in [2, 4, 11] (e.g. Figures 1 and 2) In brief: A Manhattan arc is a line segment oriented at a 45 degree angle from the coordinate axes. A tilted rectangular region, or TRR, consists of all points within some fixed distance r of a core Manhattan arc. c(S 0 ) is the midpoint of the Manhattan arc ....

....are marked non planar. As long as the ZST T has a nonplanar node, Elmore Planar DME iterates at Steps 7 and 8. Note that Step 7 constructs the merging tree TS only for non planar nodes in the upper part of the ZST; Step 8 calls the top down embedding phase of DME ( Find Exact Placements(T S) in [2, 4]) to embed the shrinking set of non planar nodes. Algorithm Elmore Planar DME (G, S) Input: Topology G; set of sinks S Output: Planar ZST T having topology G 1. ZST T = DME(G,S) 2. for each v 2 T 3. if v is a sink 4. mark v planar else 5. mark v non planar 6. while T still has a non planar ....

[Article contains additional citation context not shown here]

T.-H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With Minimum Wirelength", IEEE Trans. on Circuits and Systems 39(11) (1992), pp. 799-814.

....under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. 1) For a fixed tree topology the Extended DME (Ex DME) approach extends the DME algorithm for exact zero skew trees [4] via the concept of a merging region. Ex DME is optimal for the infinite skew limiting case. 2) For arbitrary topology and arbitrary embedding, we develop the Extended Greedy DME (ExG DME) algorithm, which very closely matches the best known heuristic for the zero skew case [6, 7] and for the ....

....tradeoff that allows good engineering solutions. 1 Introduction In routing design for high performance VLSI systems, control of signal delay has become a dominant objective. For clock distribution, approaches to zero skew routing have spanned the range from highly geometric perspectives (e.g. [4, 6]) to system architecture perspectives (e.g. 10] Controlling the skew of signal arrival times is also of increasing interest for large global routes on chip or on MCM substrates. At the same time, other objectives also require attention. Certainly, the routing design should have low wiring area ....

[Article contains additional citation context not shown here]

T.-H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With Minimum Wirelength", IEEE Trans. on Circuits and Systems 39(11), November 1992, pp. 799-814.

....given, then we arbitrarily set clk = c(S) S 1 and S 2 will be confined within P S 1 and P S 2 , respectively. We conclude that no routing crosses any other. 3 The Elmore Planar DME Algorithm Several works on clock tree design use the Elmore delay model, which is more accurate than linear delay [4, 5, 6, 12]. In this section, we sketch a simple method which is the first to achieve a single layer Elmore ZST, i.e. a ZST under the Elmore delay model. Note that under the Elmore delay model, the DME algorithm is no longer optimal: it does not necessarily return a minimumcost ZST for given S and G [3, ....

....6, 12] In this section, we sketch a simple method which is the first to achieve a single layer Elmore ZST, i.e. a ZST under the Elmore delay model. Note that under the Elmore delay model, the DME algorithm is no longer optimal: it does not necessarily return a minimumcost ZST for given S and G [3, 5]. 5 Also, the merging segment for the root of the subtree over S 0 S in the DME solution is no longer independent of the subtree connection topology. Hence, the bottom up DME phase cannot be eliminated, i.e. Single Pass DME cannot be applied to the Elmore delay model. To construct a ....

[Article contains additional citation context not shown here]

T.-H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With Minimum Wirelength", IEEE Trans. on Circuits and Systems 39(11) (1992), pp. 799-814.

....B, find a routing topology G and a minimum cost clock tree TG (S) that satisfies skew(TG (S) B. 1.1. The Extended DME Algorithm The BST problem has been previously addressed in [16] 11] 9] Their basic method, called the Extended DME (Ex DME) algorithm, extends the DME algorithm of [3] [6], 5] 12] via the enabling concept of merging region, which is a set of embedding points with feasible skew and minimum merging cost if no detour wiring occurs 1 . For a fixed tree topology, Ex DME follows the 2 phase approach of the DME algorithm in constructing a bounded skew tree: i) a ....

T.-H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Trans. Circuits and Systems, 39(11):799--814, November 1992.

....G, the DME algorithm produces a ZST T in the linear model with minimum cost over all ZSTs with topology G and sinks S. DME also produces the optimal ZST in the variation of the Zero Skew Clock Routing Problem where the position of the source is fixed. This extension to Theorem 1 is proved in [4]. Under the linear model, DME also minimizes the source sink delay in a ZST. We now prove that given any input topology, DME will in fact construct a ZST with delay equal to one half the diameter of the sink set S, which is the minimum feasible radius for any tree connecting S. Define a Manhattan ....

....) d=2, which proves the theorem. 5 Suboptimality For Elmore Delay While the experimental results in Section 6 clearly show the effectiveness of the DME algorithm in the Elmore delay model, examples exist for which DME does not give an optimal ZST under the Elmore model for a given topology [2][4]. The counterexample in [2] 4] refutes the claim in [3] that the DME algorithm is optimal for any given routing topology under the Elmore model. 6 Results We implemented the DME algorithm on Sun SPARC workstations in the C UNIX environment. The code can be obtained from the authors. We used two ....

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T.-H. Chao, Y.-C. Hsu J.-M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With Minimum Wirelength," submitted to IEEE Transactions on Computers and Systems, 1992.

....and power dissipation. Thus, the zero skew clock tree and performance driven routing literatures have seen rapid growth over the past several years; see [Kahng and Robins 1994] for a detailed review. Recent works have accomplished exact zero skew under the Elmore delay model [Tsay 1993; Chao et al. 1992b; Edahiro 1993a] The Deferred Merge Embedding (DME) algorithm by [Chao et al. 1992b; Edahiro 1992] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Edahiro 1993a] Recent works have also given ....

....routing literatures have seen rapid growth over the past several years; see [Kahng and Robins 1994] for a detailed review. Recent works have accomplished exact zero skew under the Elmore delay model [Tsay 1993; Chao et al. 1992b; Edahiro 1993a] The Deferred Merge Embedding (DME) algorithm by [Chao et al. 1992b; Edahiro 1992] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Edahiro 1993a] Recent works have also given new methods for single layer (planar) clock routing [Zhu and Dai 1996; Kahng and Tsao ....

[Article contains additional citation context not shown here]

Chao, T.-H., Hsu, Y.-C. H., Ho, J.-M., Boese, K. D., and Kahng, A. B. 1992. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circuits and Systems 39, 11 (Nov.), 799--814.

....Cadence Design Systems. A. B. Kahng is currently Visiting Scientist (on sabbatical leave from UCLA) and C. W. A. Tsao is Senior Member of Technical Staff, at Cadence. The BST problem has been previously addressed in [12, 4, 3] The basic Extended DME (Ex DME) approach extends the DME algorithm [2, 5] via the concept of a merging region, which is a set of embedding points with feasible skew and minimum merging cost if no detour wiring occurs. For a fixed tree topology, Ex DME follows the 2 phase approach of the DME algorithm in constructing a bounded skew tree: i) a bottom up phase to ....

T.-H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength", IEEE Trans. Circuits and Systems, 39(11):799--814, November 1992.

....accurate control of Elmore delay skew, and show the utility of merging points inside merging regions. 1 Introduction Control of signal delay is important in layout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model [17, 5, 11], and given new single layer (planar) constructions [18, 15, 16] A detailed review of clock tree and Steiner routing algorithms is given in [14] In practice, circuits will operate correctly within a given skew tolerance, and indeed exact zero skew is never an actual design requirement [14] ....

T.-H. Chao, Y.-C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With MinimumWirelength," IEEE Trans. on Circuits and Systems 39(11), Nov. 1992, pp. 799--814.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst., vol. 39, pp. 799--814, Nov. 1992.

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T.-H. Chao, Y.-C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems, 39(11), Nov. 1992, pp. 799--814.

No context found.

T.-H. Chao, Y.-C. Hsu, J.-M. Ho, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst. II, vol. 39, pp. 799--814, Nov. 1992.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero Skew Clock Routing with Minimum Wirelength", IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. CAS-39, No. 11, pp. 799-814, November, 1992.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst. II, vol. 39, pp. 799--814, 1992.

No context found.

T.-H. Chao, Y.-C. Hsu, J.-M Ho, and A. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst. II, vol. 39, pp. 799--814, Nov. 1992.

No context found.

Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho, and A.B. Kahng. Zero skew clock routing with minimum wirelength. Circuits and Systems II: Analog and Digital Signal Processing, Volumn 39, Issue 11:799--814, Nov. 1992.

No context found.

Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho, and A.B. Kahng. Zero skew clock routing with minimum wirelength. Circuits and Systems II: Analog and Digital Signal Processing, Volumn 39, Issue 11:799--814, Nov. 1992.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, A. B. Khang, "Zero Skew Clock Routing with Minimum Wirelength," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 39, No. 11, pp. 799-814, November 1992.

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T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Transactions on Circuits and Systems - Analog and Digital Signal Processing, 39(11):799--814, November 1992.

No context found.

T.- H. Chao, Y.-C. Hsu, J. -M. Ho, K. D. Boese, and A. B. Kahng. "Zero Skew Clock Routing with Minimum Wirelength, " IEEE Transactions Circuits Systems II: Analog and Digital Signal Processing, Vol. 39, No. 11, pp. 799-814, November 1992.

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T. Chao, et al., "Zero Skew Clock Routing with Minimum Wirelength," IEEE Trans. Circuits Syst.-II, vol. 39, no. 11, pp. 799-814, Nov. 1992.

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T.-H. Chao, Y.-C. Hsu Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Trans. on Circuits and Systems, 39(11):799-- 814, November 1992.

No context found.

T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero Skew Clock Routing with Minimum Wirelength, " IEEE Trans. on Circuits and Systems, Vol. 39, No. 11, pp. 799-814, November 1992.

No context found.

T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero Skew Clock Routing with Minimum Wirelength," IEEE Trans. on Circuits and Systems, Vol. 39, No. 11, pp. 799-814, November 1992.

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