K. D. Boese and A. B. Kahng, "Zero-skew clock routing trees with minimum wirelength," in Proc. IEEE Int. Conf. ASIC, 1992, pp. 1.1.1--1.1.5.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....and about 32 using a single external supply voltage. 1. INTRODUCTION The clock network constitutes one of the most important parts of a synchronous VLSI chip as it can significantly influence the speed, area, and power dissipation of the system. Recent research on clock network construction [2,3,5,6,10,11,13,14,15] has developed procedures for building a zero or near zero skew clock network with sharp clock edge rates at the clock utilization points. However, one major drawback associated with clock networks is their power dissipation. Studies have shown that the clock network can dissipate 20 50 of the ....

....bottom up combination of two zero skew subtrees by finding a tapping point to ensure zero skew in the larger subtree thus formed. While Tsay s algorithm suggested a framework to build zero skew subtrees, it did not try to minimize the total wire length. The Deferred Merged Embedding (DME) method [2,3,5] optimally embeds a given clock tree topology in the Manhattan plane with zero skew and attempts to minimize the total wire length. In addition to zero skew, a second requirement on a clock tree is that the slew rate for the clock edge must be sharp. This requires the insertion of This research ....

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K. D. Boese and A. B. Kahng. "Zero-Skew Clock Routing Trees With Minimum Wire length," Proceedings of the IEEE International Conference on ASIC, pp. 1.1.11. 1.5, 1992.

....a clock schedule that achieves a smaller clock period and that can be realized with the wire length at least comparable to or smaller than that of a zero skew clock tree. Many clock tree algorithms have been proposed to reduce the wire length and power consumption under the framework of zero skew [2, 3, 4, 9, 10], bounded skew [6, 7, 12] useful skew [21, 22] and associative skew [5] However, they did not fully utilize the flexibility of clock schedule. The flexibility is utilized to improve the circuit performance by combining the retiming in [16] and to improve the circuit reliability in [14] ....

K. D. Boese and A. B. Kahng. Zero-skew clock routing trees with minimum wirelength. In Proc. IEEE 5th ASIC Conf., pages 1.1.1--1.1.5, 1992.

....can be obtained by radius minimization, with direct paths between the driver and all sink nodes. Shortest path trees rooted at the source achieve this goal. A number of works address the radius objectives, both for general path length minimization, and also for skew minimization in clock nets [3], 6] 13] 20] A minimum radius construction with a suitable root point may be also be a minimum diameter construction. When there are multiple sources and sinks, path length minimization can be achieved by minimizing the maximum distance between any pair of nodes, which leads to diameter o ....

.... s which contain the rectangle. connecting the center of the circle to each point in the set was shown to have the minimum diameter possible of any Steiner tree over the points. We follow their general approach, but address the Manhattan plane and also pursue tree length minimization. The work in [3], 6] 13] and [20] can be used to construct minimum diameter trees, but they are concerned mainly with skew minimization instead of total tree length minimization. The Manhattan minimum diameter Steiner tree problem has not been explicitly studied in the literature. Our work studies the ....

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K. D. Boese and A. B. Kahng, "Zero-skew clock routing trees with minimum wirelength," in Proc. IEEE Int. Conf. ASIC, 1992, pp. 1.1.1--1.1.5.

.... restriction of the BST problem to the rectilinear plane is also known to be NP hard, but the complexity of the rectilinear ZST problem is not known for a fixed tree topology the problem can be solved in linear time by using the Deferred Merge Embedding (DME) algorithm independently introduced in [6, 7, 11]. Although the rectilinear zero and bounded skew tree problems have received much attention in the VLSI CAD literature [4, 6, 7, 8, 10, 11, 12, 16, 17, 20] see Chapter 4 of [18] 2 for a detailed review) the first algorithms with constant approximation factors have been proposed only recently, ....

.... is not known for a fixed tree topology the problem can be solved in linear time by using the Deferred Merge Embedding (DME) algorithm independently introduced in [6, 7, 11] Although the rectilinear zero and bounded skew tree problems have received much attention in the VLSI CAD literature [4, 6, 7, 8, 10, 11, 12, 16, 17, 20] (see Chapter 4 of [18] 2 for a detailed review) the first algorithms with constant approximation factors have been proposed only recently, by Charikar et al. 9] They give algorithms with approximation factors of 2e 5:44 and 16.86 for ZST and BST problems, respectively. The BST algorithm in ....

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BOESE, K., AND KAHNG, A. Zero-skew clock routing trees with minimum wirelength. In Proc. IEEE International ASIC Conf. (1992), pp. 17--21.

....of which are non redundant in terms of phase delay and wirelength. We show that our algorithm provides a sound tradeoff between phase delay and wire length. In [Tsa91] a bottom up merging scheme which ensures zero skew under Elmore delay model [Elm48] is proposed. Later three research groups [BK92, CHH92, Eda91] independently propose a two phase method (bottomup merging phase and top down embedding phase) for clock tree routing assuming tree topology is given. This method is called Deferred Merging Embedding (DME) algorithm. To determine tree topology, in [Eda93, Eda94] a clustering bottom up algorithm ....

K.D. Boose and A.B. Kahng, "Zero-skew clock routing trees with minimum wirelength," Proc. IEEE Intl. Conf. on ASIC, pp.1.1.1-1.1.5, 1992.

.... restriction of the BST problem to the rectilinear plane is also known to be NP hard, but the complexity of the rectilinear ZST problem is not known for a fixed tree topology the problem can be solved in linear time by using the Deferred Merge Embedding (DME) algorithm independently introduced in [6, 7, 11]. Although the rectilinear zero and bounded skew tree problems have received much attention in the VLSI CAD literature [4, 6, 7, 8, 10, 11, 12, 16, 17, 20] see Chapter 4 of [18] for a detailed review) the first algorithms with constant approximation factors have been proposed only recently, by ....

.... is not known for a fixed tree topology the problem can be solved in linear time by using the Deferred Merge Embedding (DME) algorithm independently introduced in [6, 7, 11] Although the rectilinear zero and bounded skew tree problems have received much attention in the VLSI CAD literature [4, 6, 7, 8, 10, 11, 12, 16, 17, 20] (see Chapter 4 of [18] for a detailed review) the first algorithms with constant approximation factors have been proposed only recently, by Charikar et al. 9] They give algorithms with approximation factors of 2e 5:44 and 16.86 for ZST and BST problems, respectively. The BST algorithm in [9] ....

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BOESE, K., AND KAHNG, A. Zero-skew clock routing trees with minimum wirelength. In Proc. IEEE International ASIC Conf. (1992), pp. 17--21.

....each of which are non redundant in terms of phase delay and wirelength. We show that our algorithm provides a sound tradeoff between phase delay and wire length. In [16] a bottom up merging scheme which ensures zero skew under Elmore delay model [10] is proposed. Later three research groups [2, 3, 8] independently propose a two phase method (bottom up merging phase and top down embedding phase) for clock tree routing 1 assuming tree topology is given. This method is called Deferred Merging Embedding (DME) algorithm. To determine tree topology, in [7, 9] a clustering bottom up algorithm ....

....our algorithm still performs better when more buffers are inserted. In order to show that the delay and wirelength values of the clock trees constructed by our algorithm are actually good, in the figures we also show the positions of the results generated by one of the previous best algorithm [2] (labeled Early ) Although doing buffer insertion causes wirelength to increase, our algorithm still manages to get very good wirelength values. Acknowledgement The authors would like to thank R. S. Tsay of ArcSys Inc. for providing benchmark data, and M. Edahiro of C C Research Lab. NEC ....

K.D. Boose and A.B. Kahng, "Zero-skew clock routing trees with minimum wirelength," Proc. IEEE Intl. Conf. on ASIC, pp.1.1.1-1.1.5, 1992.

....Lemma 3 cost(T ) can be decreased, contradicting the assumption that T has minimum cost. It can be proved that in the linear model, DME also minimizes the source sink delay in a ZST, and that this delay is equal to one half the diameter of the sink set S. A proof of this result is contained in [3]. The DME algorithm is also optimal for any topology in the variant of the ZST problem where the source location is pre defined. Suppose that ms(s 0 ) is the merging segment for the root node s 0 of topology G and that s 0 0 is the prescribed source location. The DME algorithm can be modified ....

....topologies produced by the KCR algorithm. The combined BB DME algorithm produced an average reduction in cost of 15 from the MMM results. We also obtained an 8 average cost reduction from the KCR algorithm. Note that in the linear model, DME also produces trees with optimal source sink delay [3], and our experiments showed an average reduction of 19 from the KCR algorithm. The improvement in source sink delay ranged from 9 for Primary1 to 23 for r3. reduction by reduction by BB DME BB DME number MMM Tsay Tsay DME KCR DME BB DME from from of sinks cost cost cost cost cost MMM ( Tsay ....

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K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE Intl. Conf. on ASIC, 1992, pp. 1.1.1 - 1.1.5.

....clock nets. For example, interconnect topologies such as bounded radius bounded cost trees [10] AHHK trees [1] maximum performance trees [8] A trees [15] low delay trees [4] and IDW CFD trees [19] have been proposed to optimize general nets. For clock nets, zero skew tree (ZST) construction [3, 5, 17] and bounded skew tree (BST) construction [13, 20, 11] have been studied extensively. Interconnect delay can be further reduced by sizing device and wire. The wiresizing algorithms in [15, 16, 9, 24, 21] can minimize interconnect delay by optimally assigning different wire width to each wire ....

K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength", Proc. IEEE 5th Int'l ASIC Conf., Rochester, September 1992, pp. 1.1.1 - 1.1.5.

....can be obtained by radius minimization, with direct paths between the driver and all sink nodes. Shortest path trees rooted at the source achieve this goal. A number of works address the radius objectives, both for general path length minimization, and also for skew minimization in clock nets[13, 3, 6, 20]. A minimum radius construction with a suitable root point may be also be a minimum diameter construction. When there are multiple sources and sinks, path length minimization can be achieved by minimizing the maximum distance between any pair of nodes, which leads to diameter minimization. Our ....

....diameter circle, a star topology connecting the center of the circle to each point in the set was shown to have the minimum diameter possible of any Steiner tree over the points. We follow their general approach, but address the Manhattan plane and also pursue tree length minimization. The work in [13, 3, 6, 20] can be used to construct minimum diameter trees, but they are concerned mainly with skew minimization instead of total tree length minimization. The Manhattan minimum diameter Steiner tree problem has not been explicitly studied in the literature. Our work studies the construction of minimum ....

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K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees with Minimum Wirelength," Proc. IEEE Int. Conf. ASIC, pp. 1.1.1-1.1.5, 1992.

.... Chapter 5 in [43] Bounded Radius Minimum Routing Tree ( 19] Chapter 3 in [43] Non Uniform Bounded Radius Minimum Routing Tree ( 20] Chapter 3 in [43] Critical Sink Routing Tree ( 9] Chapter 3 in [43] Elmore Delay Optimal Steiner Tree ( 8] Chapter 3 in [43] Zero Skew Clock Routing Tree ([7], Chapter 4 in [43] Pathlength Balanced Tree (Chapter 4 in [43] Bounded Skew Routing Trees with Elmore Delay Formulations ( 7] Chapter 4 in [43] 3 The CMST Problem and Its Variants Besides centralized communication network design [47] the CMST problem has also been employed in vehicle ....

.... ( 20] Chapter 3 in [43] Critical Sink Routing Tree ( 9] Chapter 3 in [43] Elmore Delay Optimal Steiner Tree ( 8] Chapter 3 in [43] Zero Skew Clock Routing Tree ( 7] Chapter 4 in [43] Pathlength Balanced Tree (Chapter 4 in [43] Bounded Skew Routing Trees with Elmore Delay Formulations ([7], Chapter 4 in [43] 3 The CMST Problem and Its Variants Besides centralized communication network design [47] the CMST problem has also been employed in vehicle routing [53] Depending on the application, several versions of the CMST problem have been studied in the literature differing in ....

K. D. Boese and A. B. Kahng. Zero-skew clock routing trees with minimum wirelength. In Proc. Intn'l ASIC Conf., pp. 17--21, 1992. Rochester, NY.

....the Elmore delay evaluation is simultaneously used to guide the bottom up path matching process. This algorithm can also handle buffered clock trees with variable loading capacitances. This algorithm may need to elongate faster paths via wire snaking as necessary. Other algorithms [CHJ 92, BK92, Eda93a, CC93, Eda94] further reduced the total wire length of the clock tree, based on the Elmore delay model. Chao, Hsu and Ho [CHJ 92] proposed a deferred merge embedding (DME) method, achieving 10 wire reduction over [Tsa91b] Boese and Kahng [BK92] independently developed an algorithm ....

....necessary. Other algorithms [CHJ 92, BK92, Eda93a, CC93, Eda94] further reduced the total wire length of the clock tree, based on the Elmore delay model. Chao, Hsu and Ho [CHJ 92] proposed a deferred merge embedding (DME) method, achieving 10 wire reduction over [Tsa91b] Boese and Kahng [BK92] independently developed an algorithm with the identical principle of the DME, achieving 12 wire reduction. Edahiro [Eda93a, Eda94] proposed a greedy DME algorithm based on the neighbor clustering, achieving 17 wire reduction, which is the best result of current zero skew clock routing ....

K.D. Boese and A.B. Kahng. Zero-skew clock routing trees with minimum wirelength. In Proc. 5th IEEE Intl. Conf. on ASIC, pages 17--21, 1992.

....schedule) at all registers more carefully; intentional clock skews are used constructively to improve system performance. Clock schedule optimization will be discussed in Section 5.6. Recent works on clock skew minimization have accomplished exact zero skew under both the pathlengthdelay model [BoKa92, Ed91, Ed92] and the Elmore delay model [Ts91, BoKa92, ChHH92a, ChHH92b] The Deferred Merge Embedding (DME) algorithm by [BoKa92, ChHH92a, Ed91] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Ed93a] The ....

....clock skews are used constructively to improve system performance. Clock schedule optimization will be discussed in Section 5.6. Recent works on clock skew minimization have accomplished exact zero skew under both the pathlengthdelay model [BoKa92, Ed91, Ed92] and the Elmore delay model [Ts91, BoKa92, ChHH92a, ChHH92b]. The Deferred Merge Embedding (DME) algorithm by [BoKa92, ChHH92a, Ed91] can be either applied to a given clock topology or combined with a clock topology generation algorithm to achieve zero skew with a smaller wirelength [Ed93a] The methods in [CoKo95, HuKT95, CoKK95] address the bounded skew ....

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K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE 5th Int'l ASIC Conf., Rochester, September 1992, pp. 1.1.1 - 1.1.5.

No context found.

BOESE, K. D., AND KAHNG, A. B. 1992. Zero-skew clock routing trees with minimum wirelength. In Proceedings of the IEEE International ASIC Conference (Sept.) 1.1.1--1.1.5.

No context found.

K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength", Proc. IEEE 5th Intl. ASIC Conf., Rochester, September1992, pp. 1.1.1 - 1.1.5.

....1948] We propose the new BST DME algorithm which, similar to the DME construction of a zero skew tree, computes a routing tree for a prescribed topology using two bottom up and top down phases. The enabling concept is a merging region, which generalizes the merging segment concept [Edahiro 1991; Boese and Kahng 1992; Chao et al. 1992a] for zero skew clock trees. Figure 1 highlights the difference between the DME algorithm for zero skew routing and our proposed BST DME algorithm for bounded skew routing. In contrast to constructing merging segments in the zero skew DME algorithm, the bottom up process of our ....

....the Elmore model, the signal delay t(u, v) is given by t#u, v# # # ew#Path#u,v# # e w # z r z # # e w # z c 2 # Cap#w# # , which can be computed in linear time recursively [Tsay 1993] 2. 1 The DME Approach The Deferred Merge Embedding (DME) algorithm was proposed independently in Boese and Kahng [1992], Chao et al. 1992a] and Edahiro [1991] It achieves exact zero skew given any delay model for which sink delays are monotone in the length of each edge of the clock tree (e.g. pathlength delay and Elmore delay) For pathlength delay, DME returns the optimal solution, that is, a tree with ....

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BOESE, K. D., AND KAHNG, A. B. 1992. Zero-skew clock routing trees with minimum wirelength. In Proceedings of the IEEE International ASIC Conference (Sept.) 1.1.1--1.1.5.

....the bounded radius, bounded cost interconnection tree algorithms of [4] 5] 6] see also the discussion of [2] which surveys previous work on the timing driven interconnection problem. Finally, the minimum clock skew problem has been extensively treated in such recent works as [11] 12] 18] [3]. We make note of these existing formulations because our proposed algorithms for minimum density interconnection trees afford unique multiple optimizations indeed, triple optimizations wherein more than one competing objective may be optimized simultaneously. Section 4 below describes ....

K. D. Boese and A. B. Kahng, Zero-Skew Clock Routing Trees with Minimum Wirelength, in Proc. IEEE Intl. ASIC Conf., Rochester, NY, September 1992, pp. 17--21.

....T . Three directions in the recent clock routing literature are relevant to our present work. ffl The zero skew tree (ZST) literature, which seeks a minimumcost clock tree having zero skew, saw rapid growth during the early 1990 s [15, 13] Notably, the Deferred Merge Embedding (DME) algorithm [1, 3, 8] embeds internal nodes of a topology G via (i) bottom up construction of a tree of merging segments, or merging tree, representing loci of possible placements of internal nodes in the ZST; and (ii) top down In memory of Mr. Patrick Catapano, Jr. of Motorola Corporation, and his contributions ....

....tree in preorder 5 stopping traversal at the marked nodes. Note that we can further improve the optimal slice merging by choosing nodes inside edges of A as heads of connecting edges similarly to the method how we choose tails inside edges of B. 3. 4 Heuristic H3: DME Merging As described in [1, 3, 8], the DME algorithm constructs an optimal ZST for a given topology. Our heuristic H3 extracts the topology of the optimal slice merging solution (H2) We then run the DME algorithm on this topology, using the offsets between sink subsets that were computed by H2. The result of H3 should be at ....

K. D. Boese and A. B. Kahng, "Zero-skew clock routing trees with minimum wirelength," Proc. IEEE Intl. Conf. on ASIC, pp. 1.1.1 -- 1.1.5, 1992.

....Pathlength Delay Andrew B. Kahng and Chung Wen Albert Tsao UCLA Computer Science Dept. Los Angeles, CA 90024 1596 USA Abstract Clock routing has become a critical issue in the layout design of high performance systems. We show that the two passes (bottom up and top down) of the DME algorithm [2, 3, 4, 8] can be replaced by a single topdown pass, which yields exactly the same (optimal) solution. From this, we develop a top down algorithm which dynamically determines and embeds the clock tree topology, such that (i) the embedding is guaranteed to be planar, and (ii) the result has provably minimum ....

....1 Introduction The placement phase of physical layout determines positions for the synchronizing elements of a circuit, which are the sinks of the clock net. Large cell based designs can have thousands of sinks in a clock net, located arbitrarily throughout the layout region. Following [2, 4], we denote the set of sink locations in a clock routing instance as S = fs 1 ; s 2 ; s ng ae 2 . A connection topology is a rooted binary tree, G, which has n leaves corresponding to the sinks in S. A clock tree T (S) is an embedding of the connection topology in the Manhattan plane, ....

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K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE Intl. Conf. on ASIC, 1992, pp. 1.1.1 - 1.1.5.

No context found.

K.D. Boese, A.B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength", in Proc. IEEE International Conf. on ASIC, 1992, pp. 1.1.1-1.1.5.

....the Manhattan plane. Several previous works achieve exact zero skew routing. Tsay [14] recursively combines pairs of zero skew trees at tapping points to induce the topology G as it is being embedded; exact zero Elmore delay skew is maintained by elongating wires as necessary. The DME algorithm [2, 3, 7] embeds internal nodes of G via (i) bottom up construction of a tree of merging segments, or merging tree, representing loci of possible placements of internal nodes in the ZST; and (ii) top down determination of exact locations for the internal nodes of G. Since DME requires an input topology, ....

....tree, representing loci of possible placements of internal nodes in the ZST; and (ii) top down determination of exact locations for the internal nodes of G. Since DME requires an input topology, several works have studied topology constructions that lead to low cost solutions when DME is applied [2, 3, 8]. Clock tree solutions given by the above algorithms may not be easily embedded in the layout plane. However, in practice clock nets are often routed with a single preferred layer, e.g. to reduce delay and attenuation through vias. Single layer routing also has more uniform electrical parameters, ....

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K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE Intl. Conf. on ASIC, 1992, pp. 1.1.1 - 1.1.5.

....heuristics in the literature for B = 0 and B = 1, and achieve a smooth tradeoff in between. Finally, Section 6 concludes with experimental results and directions for future work. 2 A Review of Three DME Variants The Deferred Merge Embedding (DME) algorithm, proposed independently by three groups [5, 3, 1, 4], achieves exact zero skew given any delay model for which sink delays are monotone in the length of each edge of the clock tree (e.g. linear delay and Elmore delay have this property) For the linear delay model, DME is optimal: it returns a tree with minimum cost and minimum source sink ....

....it returns a tree with minimum cost and minimum source sink pathlength for any input sink set S and topology G. Because the properties of the DME construction are central to our present work, we review key details of DME and its Greedy DME and Planar DME variants, following the developments in [1, 15]. In the following discussion, we identify each node v of the rooted topology G with the edge e v to its parent. Once a node v of the topology has been embedded in the Manhattan plane, we often identify v with its location in the plane, denoted l(v) The cost of a routing tree T is defined as ....

[Article contains additional citation context not shown here]

K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE Intl. Conf. on ASIC, 1992, pp. 1.1.1 - 1.1.5.

....elongated via snaking as necessary. The above methods all concentrate on generation of the clock tree topology: the topology is then embedded in the plane more or less arbitrarily as it is generated. The Deferred Merge Embedding (DME) method, which was discovered independently by three groups [3, 4, 11], is a linear time algorithm which optimally embeds any given topology in the Manhattan plane, i.e. with exact zero skew and minimum total wirelength. Because the properties of the DME construction are central to our present work, we now provide a review of DME following the development in [3] ....

....4, 11] is a linear time algorithm which optimally embeds any given topology in the Manhattan plane, i.e. with exact zero skew and minimum total wirelength. Because the properties of the DME construction are central to our present work, we now provide a review of DME following the development in [3]. The DME Algorithm Given sink set S and topology G, DME embeds internal nodes of G via: i) a bottom up phase that constructs a tree of merging segments which represent loci of possible placements of internal nodes in the ZST T ; and (ii) a top down embedding phase that determines exact ....

[Article contains additional citation context not shown here]

K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE Intl. Conf. on ASIC, 1992, pp. 1.1.1 - 1.1.5.

.... of these objectives has engendered an extensive literature: the first corresponds to the minimum rectilinear Steiner tree problem [9] 12] the second has been treated in the bounded radius, bounded cost interconnection tree algorithms of [2] 4] 5] 6] and the third has been studied in, e.g. [3] [10] 11] 14] We make note of these existing formulations because our proposed algorithms for minimum density interconnection trees afford unique multiple optimizations wherein more than one competing objective may be addressed simultaneously, as discussed below. 2 Heuristics for MDIT We ....

K. D. Boese and A. B. Kahng, Zero-Skew Clock Routing Trees with Minimum Wirelength, in Proc. IEEE Intl. ASIC Conf., Rochester, NY, September 1992, pp. 17--21.

....bound B, find a routing topology G and a minimum cost clock tree TG (S) that satisfies skew(TG (S) B. 1.1. The Extended DME Algorithm The BST problem has been previously addressed in [16] 11] 9] Their basic method, called the Extended DME (Ex DME) algorithm, extends the DME algorithm of [3], 6] 5] 12] via the enabling concept of merging region, which is a set of embedding points with feasible skew and minimum merging cost if no detour wiring occurs 1 . For a fixed tree topology, Ex DME follows the 2 phase approach of the DME algorithm in constructing a bounded skew tree: i) ....

K. D. Boese and A. B. Kahng. Zero-skew clock routing trees with minimum wirelength. In Proc. IEEE Intl. Conf. on ASIC, pages 1.1.1 -- 1.1.5, 1992. 16 Andrew B. Kahng and C.-W. Albert Tsao

....the maximum pathlength skew, i.e. difference in source sink pathlengths, captures both the clock skew minimization problem as well as the min max timing constraints which arise in global routing of very high performance designs. These formulations have been treated in such recent works as [7] [17] 18] 23] We make note of these existing formulations because our proposed algorithms for minimum density inter3 connection trees afford unique multiple optimizations wherein up to three competing objectives may be optimized simultaneously. As a result, the area minimization objective of ....

K. D. Boese and A. B. Kahng, Zero-Skew Clock Routing Trees with Minimum Wirelength, in Proc. IEEE Intl. ASIC Conf., Rochester, NY, September 1992, pp. 17--21.

....routing, or in fully exploiting the available skewbound B. For this variant, in either the non planar or the planar case, we typically assume that the source location s 0 is also unspecified. 2 A Review of Three DME Variants The Deferred Merge Embedding (DME) algorithm, proposed independently in [5, 3, 1], achieves exact zero skew given any delay model for which sink delays are monotone in the length of each edge of the clock tree (e.g. linear delay and Elmore delay) For linear delay, DME is optimal: it returns a tree with minimum cost and minimum source sink pathlength for any input sink set S ....

....length of each edge of the clock tree (e.g. linear delay and Elmore delay) For linear delay, DME is optimal: it returns a tree with minimum cost and minimum source sink pathlength for any input sink set S and topology G. We now review DME and its Greedy DME and Planar DME variants, following [1, 14]. We identify each node v of the rooted topology G with the edge ev to its parent. Once a node v of the topology has been embedded in the Manhattan plane, we often identify v with its location in the plane, denoted l(v) The cost of a routing tree T is defined as cost(T ) P v2T jev j, i.e. ....

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K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With MinimumWirelength," Proc. IEEE Intl. Conf. onASIC, 1992, pp. 1.1.1 - 1.1.5.

....[Elmore 1948] We propose the new BST DME algorithm which, similar to the DME construction of a zero skew tree, computes a routing tree for a prescribed topology using two bottom up and top down phases. The enabling concept is a merging region, which generalizes the merging segment concept of [Boese and Kahng 1992; Chao et al. 1992a; Edahiro 1991] for zero skew clock trees. Fig. 1 highlights the difference between the DME algorithm for zero skew routing and our proposed BST DME algorithm for bounded skew routing. In contrast to constructing merging segments in the zero skew DME algorithm, the bottom up ....

....the Elmore model the signal delay t(u; v) is given by t(u; v) X ew2Path(u;v) je w j Delta r Delta ( je w j Delta c 2 Cap(w) which can be computed in linear time recursively [Tsay 1993] 2. 1 The DME Approach The Deferred Merge Embedding (DME) algorithm, proposed independently in [Boese and Kahng 1992; Chao et al. 1992a; Edahiro 1991] achieves exact zero skew given any delay model for which sink delays are monotone in the length of each edge of the clock tree (e.g. pathlength delay and Elmore delay) For pathlength delay, DME returns the optimal solution, i.e. a tree with minimum cost and ....

[Article contains additional citation context not shown here]

Boese, K. D. and Kahng, A. B. 1992. Zero-skew clock routing trees with minimum wirelength. In Proc. IEEE Int. ASIC Conf. (Sept. 1992). pp. 1.1.1--1.1.5.

....tree routing, for performance driven Steiner routing, and even for power distribution topology design [31] a bounded skew routing tree formulation applies. Recent works [10, 19] have studied this problem under the pathlength (linear) delay model, and generalized the DME clock routing construction [2, 5, 13] via the concept of a merging region. However, in practice bounding the pathlength skew does not allow reliable control of actual delay skew, e.g. withrespect to the Elmore delay approximation. Thus, in this workwe study the minimum costbounded skew routing tree problem under the Elmore delay ....

....two recent works [10, 19] have addressed the BST problem, and proposed clock and Steiner global routing algorithms that construct BSTs under the linear, i.e. pathlength, delay model. The enabling concept in [10, 19] is that of a merging region, which generalizes the merging segment concept of [2, 5, 13] for zeroskew clock trees. Unfortunately, in practice we find that bounding the pathlength skew does not afford any reliable control of the actual delay skew. Figure 1(a) shows HSPICE delay skew against pathlength delay skew for routing trees generated by the ExG DME algorithm [19] on the r1 5 ....

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K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength", Proc. IEEE 5th Int'l ASIC Conf., Rochester, September 1992, pp. 1.1.1 - 1.1.5.

....have addressed the bounded skew routing tree (BST) problem, and proposed clock and Steiner global routing algorithms that construct BSTs under the linear, i.e. pathlength, delay model. The enabling concept in [8, 12] is that of a merging region, which generalizes the merging segment concept of [1, 4, 10] for zeroskew clock trees. 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 7000 0 50 100 150 200 250 HSPICE Skew (ps) Pathlength Skew ( m) 3 3 3 3 3 3 3 3 3 0 100 200 300 400 500 600 0 100 200 300 400 500 HSPICE Skew (ps) Elmore Skew (ps) 3 3 3 3 3 3 3 3 3 3 3 (a) b) Figure 1: Plots of (a) ....

....Path(u;v) denote the unique u v path. Then, Elmore delay between nodes u and v is given by t(u;v) e w 2Path(u;v) r w Delta ( c w 2 C w ) DME Based Heuristics The methods of [8, 12] as well as those we propose below, are generalizations of the Deferred Merge Embedding (DME) algorithm [1, 4, 10]. Given S and G, DME embeds internal nodes of G via: i) a bottom up phase that constructs a tree of merging segments which represent loci of possible placements of internal nodes in a zero skew tree (ZST) T ; and (ii) a top down embedding phase that determines exact locations for the internal ....

K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength", Proc. IEEE 5th Intl. ASIC Conf., Rochester, September1992, pp. 1.1.1 - 1.1.5.

No context found.

K. D. Boese and A. B. Kahng, "Zero-skew clock routing trees with minimum wirelength," in Proc. IEEE Int. Conf. ASIC, 1992, pp. 1.1.1--1.1.5.

No context found.

Kenneth D. Boese and Adrew B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE International Conference on ASIC, pp. 1.1.1-1.1.5, 1992.

No context found.

Kenneth D. Boese and Adrew B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. of IEEE International Conference on ASIC, pp. 1.1.1-1.1.5, 1992.

No context found.

Kenneth D. Boese and Adrew B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE International Conference on ASIC, pp. 1.1.1-1.1.5, 1992.

No context found.

Kenneth D. Boese and Adrew B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE International Conference on ASIC, pp. 1.1.1-1.1.5, 1992.

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